{"id":"https://openalex.org/W2017715965","doi":"https://doi.org/10.1145/258305.258320","title":"Synthesis and floorplanning for large hierarchical FPGAs","display_name":"Synthesis and floorplanning for large hierarchical FPGAs","publication_year":1997,"publication_date":"1997-01-01","ids":{"openalex":"https://openalex.org/W2017715965","doi":"https://doi.org/10.1145/258305.258320","mag":"2017715965"},"language":"en","primary_location":{"id":"doi:10.1145/258305.258320","doi":"https://doi.org/10.1145/258305.258320","is_oa":true,"landing_page_url":"https://doi.org/10.1145/258305.258320","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/258305.258320","source":{"id":"https://openalex.org/S7407087960","display_name":"ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays - FPGA '97","raw_type":"proceedings-article"},"volume":null,"type":"conference-paper","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"bronze","oa_url":"https://dl.acm.org/doi/pdf/10.1145/258305.258320","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5002627363","display_name":"Helena Krupnova","orcid":"https://orcid.org/0009-0005-2682-1653","observed_orcids":["https://orcid.org/0009-0005-2682-1653"]},"institutions":[{"id":"https://openalex.org/I106785703","display_name":"Institut polytechnique de Grenoble","ror":"https://ror.org/05sbt2524","country_code":"FR","type":"education","lineage":["https://openalex.org/I106785703","https://openalex.org/I899635006"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"H. Krupnova","raw_affiliation_strings":["Institute National Polytechnique de Grenoble/CSI, 46, Avenue Felix Viallet, 38031 Grenoble, Cedex France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute National Polytechnique de Grenoble/CSI, 46, Avenue Felix Viallet, 38031 Grenoble, Cedex France","institution_ids":["https://openalex.org/I106785703"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5015384460","display_name":"C. Rabedaoro","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I106785703","display_name":"Institut polytechnique de Grenoble","ror":"https://ror.org/05sbt2524","country_code":"FR","type":"education","lineage":["https://openalex.org/I106785703","https://openalex.org/I899635006"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"C. Rabedaoro","raw_affiliation_strings":["Institute National Polytechnique de Grenoble/CSI, 46, Avenue Felix Viallet, 38031 Grenoble, Cedex France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute National Polytechnique de Grenoble/CSI, 46, Avenue Felix Viallet, 38031 Grenoble, Cedex France","institution_ids":["https://openalex.org/I106785703"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5110070055","display_name":"G. Saucier","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I106785703","display_name":"Institut polytechnique de Grenoble","ror":"https://ror.org/05sbt2524","country_code":"FR","type":"education","lineage":["https://openalex.org/I106785703","https://openalex.org/I899635006"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"G. Saucier","raw_affiliation_strings":["Institute National Polytechnique de Grenoble/CSI, 46, Avenue Felix Viallet, 38031 Grenoble, Cedex France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute National Polytechnique de Grenoble/CSI, 46, Avenue Felix Viallet, 38031 Grenoble, Cedex France","institution_ids":["https://openalex.org/I106785703"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I106785703"],"apc_list":null,"apc_paid":null,"fwci":14.2967,"has_fulltext":true,"cited_by_count":21,"citation_normalized_percentile":{"value":0.99224506,"is_in_top_1_percent":true,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":88,"max":93},"biblio":{"volume":null,"issue":null,"first_page":"105","last_page":"111"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9976000189781189,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9976000189781189,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.0017000000225380063,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13292","display_name":"Embedded Systems and FPGA Applications","score":9.999999747378752e-05,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/floorplanning","display_name":"floorplanning","score":0.9039999842643738},{"id":"https://openalex.org/keywords/hierarchical-design","display_name":"hierarchical design","score":0.3619999885559082},{"id":"https://openalex.org/keywords/fpga-synthesis","display_name":"FPGA synthesis","score":0.5099999904632568}],"concepts":[{"id":"https://openalex.org/C130145326","wikidata":"https://www.wikidata.org/wiki/Q1553985","display_name":"Floorplan","level":2,"score":0.9782545566558838},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7860259413719177},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7538051605224609},{"id":"https://openalex.org/C166955791","wikidata":"https://www.wikidata.org/wiki/Q629579","display_name":"Macro","level":2,"score":0.7211369872093201},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.6435091495513916},{"id":"https://openalex.org/C31170391","wikidata":"https://www.wikidata.org/wiki/Q188619","display_name":"Hierarchy","level":2,"score":0.6121810674667358},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5132558345794678},{"id":"https://openalex.org/C2765594","wikidata":"https://www.wikidata.org/wiki/Q2624187","display_name":"Integrated circuit layout","level":3,"score":0.49568045139312744},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.48448798060417175},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.4424899220466614},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.435786634683609},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.43278640508651733},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.34311169385910034},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.32438063621520996},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.30405259132385254},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2963566780090332},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.11718985438346863},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C34447519","wikidata":"https://www.wikidata.org/wiki/Q179522","display_name":"Market economy","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/258305.258320","doi":"https://doi.org/10.1145/258305.258320","is_oa":true,"landing_page_url":"https://doi.org/10.1145/258305.258320","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/258305.258320","source":{"id":"https://openalex.org/S7407087960","display_name":"ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays - FPGA '97","raw_type":"proceedings-article"}],"best_oa_location":{"id":"doi:10.1145/258305.258320","doi":"https://doi.org/10.1145/258305.258320","is_oa":true,"landing_page_url":"https://doi.org/10.1145/258305.258320","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/258305.258320","source":{"id":"https://openalex.org/S7407087960","display_name":"ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays - FPGA '97","raw_type":"proceedings-article"},"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"grobid_xml":true,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2017715965.pdf","grobid_xml":"https://content.openalex.org/works/W2017715965.grobid-xml"},"referenced_works_count":7,"referenced_works":["https://openalex.org/W2010346244","https://openalex.org/W2021371375","https://openalex.org/W2060509365","https://openalex.org/W2101007244","https://openalex.org/W2104842639","https://openalex.org/W2174422527","https://openalex.org/W4236269389"],"related_works":["https://openalex.org/W2154940055","https://openalex.org/W1989421651","https://openalex.org/W7099002079","https://openalex.org/W2101542926","https://openalex.org/W82219846","https://openalex.org/W1986643492","https://openalex.org/W7096951795","https://openalex.org/W1500177650","https://openalex.org/W2180598069","https://openalex.org/W2986737380"],"abstract_inverted_index":{"Because":[0],"the":[1,6,27,60,63,66,69,76,82,97],"VLSI":[2],"circuits":[3,16],"complexity":[4],"growth,":[5],"trend":[7],"in":[8,14],"design":[9,64],"is":[10,85],"towards":[11],"divide-and-conquer":[12],"schemes,":[13],"which":[15,55],"are":[17,42],"composed":[18],"of":[19,34,62,68,81,90],"blocks,":[20],"standard":[21],"macros":[22],"or":[23],"custom":[24],"macros.":[25],"From":[26],"other":[28],"side,":[29],"to":[30,96],"allow":[31],"an":[32],"implementation":[33],"large":[35],"digital":[36],"circuits,":[37],"increased":[38],"capacity":[39],"target":[40,98],"FPGAs":[41],"organized":[43],"hierarchically.":[44],"In":[45],"this":[46],"paper,":[47],"we":[48],"present":[49],"a":[50],"hierarchical":[51,100],"FPGA":[52,99],"floorplanning":[53],"method":[54,72],"takes":[56],"into":[57],"account":[58],"both":[59],"hierarchy":[61,67],"and":[65,78,84,93],"target.":[70],"The":[71],"aims":[73],"at":[74],"minimization":[75],"timing":[77],"balancing":[79],"cost":[80],"floorplan":[83],"based":[86],"on":[87],"automatic":[88],"detection":[89],"macro":[91],"blocks":[92],"assigning":[94],"them":[95],"zones.":[101]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2015,"cited_by_count":1}],"updated_date":"2026-11-07T11:25:07.637180","created_date":"2016-06-24T00:00:00"}