{"id":"https://openalex.org/W2017398386","doi":"https://doi.org/10.1080/00207217.2014.897381","title":"Multiplier less high-speed squaring circuit for binary numbers","display_name":"Multiplier less high-speed squaring circuit for binary numbers","publication_year":2014,"publication_date":"2014-03-19","ids":{"openalex":"https://openalex.org/W2017398386","doi":"https://doi.org/10.1080/00207217.2014.897381","mag":"2017398386"},"language":"en","primary_location":{"id":"doi:10.1080/00207217.2014.897381","doi":"https://doi.org/10.1080/00207217.2014.897381","is_oa":false,"landing_page_url":"https://doi.org/10.1080/00207217.2014.897381","pdf_url":null,"source":{"id":"https://openalex.org/S36304393","display_name":"International Journal of Electronics","issn_l":"0020-7217","issn":["0020-7217","1362-3060"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core","dongbi-c","jufo-1","norway-1","poland-70","russia-white-list-2"],"host_organization":"https://openalex.org/P4310320547","host_organization_name":"Taylor & Francis","host_organization_lineage":["https://openalex.org/P4310320547","https://openalex.org/P4310320449"],"host_organization_lineage_names":["Taylor & Francis","Informa"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Journal of Electronics","raw_type":"journal-article"},"volume":null,"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5071628641","display_name":"Kabiraj Sethi","orcid":"https://orcid.org/0000-0002-6400-1729","observed_orcids":["https://orcid.org/0000-0002-6400-1729"]},"institutions":[{"id":"https://openalex.org/I185065464","display_name":"Veer Surendra Sai University of Technology","ror":"https://ror.org/02yghbg68","country_code":"IN","type":"education","lineage":["https://openalex.org/I185065464"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Kabiraj Sethi","raw_affiliation_strings":["Department of Electronics and Telecommunication Engineering, Veer Surendra Sai University of Technology, Burla 768018, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics and Telecommunication Engineering, Veer Surendra Sai University of Technology, Burla 768018, India","institution_ids":["https://openalex.org/I185065464"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5072703440","display_name":"Rutuparna Panda","orcid":"https://orcid.org/0000-0002-8676-0144","observed_orcids":["https://orcid.org/0000-0002-8676-0144"]},"institutions":[{"id":"https://openalex.org/I185065464","display_name":"Veer Surendra Sai University of Technology","ror":"https://ror.org/02yghbg68","country_code":"IN","type":"education","lineage":["https://openalex.org/I185065464"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Rutuparna Panda","raw_affiliation_strings":["Department of Electronics and Telecommunication Engineering, Veer Surendra Sai University of Technology, Burla 768018, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics and Telecommunication Engineering, Veer Surendra Sai University of Technology, Burla 768018, India","institution_ids":["https://openalex.org/I185065464"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5072703440"],"corresponding_institution_ids":["https://openalex.org/I185065464"],"apc_list":null,"apc_paid":null,"fwci":5.5286,"has_fulltext":false,"cited_by_count":23,"citation_normalized_percentile":{"value":0.95637062,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":"102","issue":"3","first_page":"433","last_page":"443"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11693","display_name":"Cryptography and Residue Arithmetic","score":0.40939998626708984,"subfield":{"id":"https://openalex.org/subfields/1710","display_name":"Information Systems"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11693","display_name":"Cryptography and Residue Arithmetic","score":0.40939998626708984,"subfield":{"id":"https://openalex.org/subfields/1710","display_name":"Information Systems"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.3292999863624573,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.17880000174045563,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/squaring-circuit","display_name":"squaring circuit","score":0.9269999861717224},{"id":"https://openalex.org/keywords/binary-numbers","display_name":"binary numbers","score":0.7670000195503235},{"id":"https://openalex.org/keywords/multiplierless-arithmetic","display_name":"multiplierless arithmetic","score":0.5619999766349792},{"id":"https://openalex.org/keywords/vedic-multiplication","display_name":"Vedic multiplication","score":0.7620000243186951},{"id":"https://openalex.org/keywords/hardware-architecture","display_name":"hardware architecture","score":0.6600000262260437},{"id":"https://openalex.org/keywords/fpga-implementation","display_name":"FPGA implementation","score":0.6470000147819519},{"id":"https://openalex.org/keywords/vedic-multiplier","display_name":"Vedic multiplier","score":0.6690000295639038},{"id":"https://openalex.org/keywords/area-time-tradeoff","display_name":"area-time tradeoff","score":0.4749999940395355}],"concepts":[{"id":"https://openalex.org/C124584101","wikidata":"https://www.wikidata.org/wiki/Q1053266","display_name":"Multiplier (economics)","level":2,"score":0.7252272963523865},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.687528133392334},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5793418288230896},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.5224912762641907},{"id":"https://openalex.org/C48372109","wikidata":"https://www.wikidata.org/wiki/Q3913","display_name":"Binary number","level":2,"score":0.514893651008606},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.46874409914016724},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4590228497982025},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.4519191086292267},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.43260475993156433},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.43023526668548584},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.4029983878135681},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3857569396495819},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.36253780126571655},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.29663020372390747},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.176383376121521},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.16438737511634827},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1221742033958435},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1080/00207217.2014.897381","doi":"https://doi.org/10.1080/00207217.2014.897381","is_oa":false,"landing_page_url":"https://doi.org/10.1080/00207217.2014.897381","pdf_url":null,"source":{"id":"https://openalex.org/S36304393","display_name":"International Journal of Electronics","issn_l":"0020-7217","issn":["0020-7217","1362-3060"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core","dongbi-c","jufo-1","norway-1","poland-70","russia-white-list-2"],"host_organization":"https://openalex.org/P4310320547","host_organization_name":"Taylor & Francis","host_organization_lineage":["https://openalex.org/P4310320547","https://openalex.org/P4310320449"],"host_organization_lineage_names":["Taylor & Francis","Informa"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Journal of Electronics","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1486006109","https://openalex.org/W1578458555","https://openalex.org/W1587217691","https://openalex.org/W1969653665","https://openalex.org/W2000920847","https://openalex.org/W2053986583","https://openalex.org/W2160520870","https://openalex.org/W2224448561","https://openalex.org/W2911296875","https://openalex.org/W4285719527"],"related_works":["https://openalex.org/W2160520870","https://openalex.org/W3020101625","https://openalex.org/W7096480955","https://openalex.org/W3010091019","https://openalex.org/W2783429107","https://openalex.org/W2783659069","https://openalex.org/W2000920847","https://openalex.org/W2182448572","https://openalex.org/W3019231110","https://openalex.org/W2737705354"],"abstract_inverted_index":{"The":[0,53,70,80,112],"squaring":[1,15,29,44,66,76,129,136],"operation":[2],"is":[3,34,47,58,62,68,78,82,103,121],"important":[4],"in":[5,8,18,36,84,90,105,114,143],"many":[6],"applications":[7],"signal":[9],"processing,":[10],"cryptography":[11],"etc.":[12],"In":[13],"general,":[14],"circuits":[16],"reported":[17],"the":[19,74],"literature":[20],"use":[21],"fast":[22],"multipliers.":[23,133],"A":[24],"novel":[25],"idea":[26],"of":[27,73,116,145],"a":[28],"circuit":[30,67,77,130,137],"without":[31],"using":[32,131],"multipliers":[33],"proposed":[35,75,135],"this":[37],"paper.":[38],"Ancient":[39],"Indian":[40],"method":[41],"used":[42],"for":[43,50],"decimal":[45],"numbers":[46],"extended":[48],"here":[49],"binary":[51],"numbers.":[52],"key":[54],"to":[55,139],"our":[56],"success":[57],"that":[59],"no":[60],"multiplier":[61],"used.":[63,69],"Instead,":[64],"one":[65],"hardware":[71],"architecture":[72],"presented.":[79],"design":[81],"coded":[83],"VHDL":[85],"and":[86,88,119,128,148],"synthesised":[87],"simulated":[89],"Xilinx":[91,106],"ISE":[92],"Design":[93],"Suite":[94],"10.1":[95],"(Xilinx":[96,110],"Inc.,":[97],"San":[98],"Jose,":[99],"CA,":[100],"USA).":[101],"It":[102],"implemented":[104],"Vertex":[107],"4vls15sf363-12":[108],"device":[109],"Inc.).":[111],"results":[113],"terms":[115,144],"time":[117],"delay":[118],"area":[120],"compared":[122],"with":[123],"both":[124,146],"modified":[125],"Booth\u2019s":[126],"algorithm":[127],"Vedic":[132],"Our":[134],"seems":[138],"have":[140],"better":[141],"performance":[142],"speed":[147],"area.":[149]},"counts_by_year":[{"year":2026,"cited_by_count":3},{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":3},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":4},{"year":2016,"cited_by_count":2}],"updated_date":"2026-10-30T12:39:25.321706","created_date":"2016-06-24T00:00:00"}