{"id":"https://openalex.org/W2017170122","doi":"https://doi.org/10.1155/2009/751687","title":"APRON: A Cellular Processor Array Simulation and Hardware Design Tool","display_name":"APRON: A Cellular Processor Array Simulation and Hardware Design Tool","publication_year":2009,"publication_date":"2009-05-07","ids":{"openalex":"https://openalex.org/W2017170122","doi":"https://doi.org/10.1155/2009/751687","mag":"2017170122"},"language":"en","primary_location":{"id":"doi:10.1155/2009/751687","doi":"https://doi.org/10.1155/2009/751687","is_oa":true,"landing_page_url":"https://doi.org/10.1155/2009/751687","pdf_url":"https://asp-eurasipjournals.springeropen.com/counter/pdf/10.1155/2009/751687","source":{"id":"https://openalex.org/S35920007","display_name":"EURASIP Journal on Advances in Signal Processing","issn_l":"1110-8657","issn":["1110-8657","1687-0433","1687-6172","1687-6180"],"is_oa":true,"is_in_doaj":true,"is_core":true,"listed_in":["anvur-scientific","cwts-core","doaj","dongbi-c","ki-jl-1","norway-1","poland-70","russia-white-list-2"],"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"EURASIP Journal on Advances in Signal Processing","raw_type":"journal-article"},"volume":null,"type":"article","is_traditional":true,"indexed_in":["crossref","doaj"],"open_access":{"is_oa":true,"oa_status":"gold","oa_url":"https://asp-eurasipjournals.springeropen.com/counter/pdf/10.1155/2009/751687","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5111664186","display_name":"David R. W. Barr","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I28407311","display_name":"University of Manchester","ror":"https://ror.org/027m9bs27","country_code":"GB","type":"education","lineage":["https://openalex.org/I28407311"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"David R.W. Barr","raw_affiliation_strings":["School of Electrical and Electronic Engineering, The University of Manchester, P. O. Box 88, Manchester, M60 1QD, UK","School of Electrical & Electronic Engineering The University of Manchester Manchester UK"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Electronic Engineering, The University of Manchester, P. O. Box 88, Manchester, M60 1QD, UK","institution_ids":["https://openalex.org/I28407311"]},{"raw_affiliation_string":"School of Electrical & Electronic Engineering The University of Manchester Manchester UK","institution_ids":["https://openalex.org/I28407311"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5057658631","display_name":"Piotr Dudek","orcid":"https://orcid.org/0000-0002-6511-6165","observed_orcids":["https://orcid.org/0000-0002-6511-6165","https://orcid.org/0000-0001-8253-9787"]},"institutions":[{"id":"https://openalex.org/I28407311","display_name":"University of Manchester","ror":"https://ror.org/027m9bs27","country_code":"GB","type":"education","lineage":["https://openalex.org/I28407311"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Piotr Dudek","raw_affiliation_strings":["School of Electrical and Electronic Engineering, The University of Manchester, P. O. Box 88, Manchester, M60 1QD, UK","School of Electrical & Electronic Engineering The University of Manchester Manchester UK"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Electronic Engineering, The University of Manchester, P. O. Box 88, Manchester, M60 1QD, UK","institution_ids":["https://openalex.org/I28407311"]},{"raw_affiliation_string":"School of Electrical & Electronic Engineering The University of Manchester Manchester UK","institution_ids":["https://openalex.org/I28407311"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5111664186"],"corresponding_institution_ids":["https://openalex.org/I28407311"],"apc_list":{"value":1790,"currency":"USD","value_usd":1790},"apc_paid":{"value":1790,"currency":"USD","value_usd":1790},"fwci":4.2197,"has_fulltext":true,"cited_by_count":23,"citation_normalized_percentile":{"value":0.93907586,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":87,"max":98},"biblio":{"volume":"2009","issue":"1","first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.6312999725341797,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.6312999725341797,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.2870999872684479,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.03269999846816063,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/hardware-design-tools","display_name":"hardware design tools","score":0.6819999814033508},{"id":"https://openalex.org/keywords/vision-chip","display_name":"vision chip","score":0.9110000133514404},{"id":"https://openalex.org/keywords/compilers","display_name":"compilers","score":0.4180000126361847},{"id":"https://openalex.org/keywords/emulation","display_name":"emulation","score":0.4909999966621399},{"id":"https://openalex.org/keywords/graphical-user-interface","display_name":"graphical user interface","score":0.6589999794960022},{"id":"https://openalex.org/keywords/development-environment","display_name":"development environment","score":0.6069999933242798}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8178825378417969},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.695328950881958},{"id":"https://openalex.org/C150552126","wikidata":"https://www.wikidata.org/wiki/Q339387","display_name":"SIMD","level":2,"score":0.6898931264877319},{"id":"https://openalex.org/C149810388","wikidata":"https://www.wikidata.org/wiki/Q5374873","display_name":"Emulation","level":2,"score":0.6377238035202026},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5489809513092041},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.5487129092216492},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5452604293823242},{"id":"https://openalex.org/C190475519","wikidata":"https://www.wikidata.org/wiki/Q544384","display_name":"Massively parallel","level":2,"score":0.5176411271095276},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.5068755745887756},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.4297229051589966},{"id":"https://openalex.org/C74366991","wikidata":"https://www.wikidata.org/wiki/Q2755335","display_name":"Network processor","level":3,"score":0.4238438904285431},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.2544308304786682},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.20077624917030334},{"id":"https://openalex.org/C157915830","wikidata":"https://www.wikidata.org/wiki/Q2928001","display_name":"Bubble","level":2,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C129307140","wikidata":"https://www.wikidata.org/wiki/Q6795880","display_name":"Maximum bubble pressure method","level":3,"score":0.0},{"id":"https://openalex.org/C50522688","wikidata":"https://www.wikidata.org/wiki/Q189833","display_name":"Economic growth","level":1,"score":0.0},{"id":"https://openalex.org/C158379750","wikidata":"https://www.wikidata.org/wiki/Q214111","display_name":"Network packet","level":2,"score":0.0}],"mesh":[],"locations_count":5,"locations":[{"id":"doi:10.1155/2009/751687","doi":"https://doi.org/10.1155/2009/751687","is_oa":true,"landing_page_url":"https://doi.org/10.1155/2009/751687","pdf_url":"https://asp-eurasipjournals.springeropen.com/counter/pdf/10.1155/2009/751687","source":{"id":"https://openalex.org/S35920007","display_name":"EURASIP Journal on Advances in Signal Processing","issn_l":"1110-8657","issn":["1110-8657","1687-0433","1687-6172","1687-6180"],"is_oa":true,"is_in_doaj":true,"is_core":true,"listed_in":["anvur-scientific","cwts-core","doaj","dongbi-c","ki-jl-1","norway-1","poland-70","russia-white-list-2"],"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"EURASIP Journal on Advances in Signal Processing","raw_type":"journal-article"},{"id":"pmh:oai:pure.atira.dk:openaire_cris_publications/a5841c58-0d9c-409c-8fa7-20ab6aab315f","doi":null,"is_oa":false,"landing_page_url":"https://research.manchester.ac.uk/en/publications/a5841c58-0d9c-409c-8fa7-20ab6aab315f","pdf_url":null,"source":{"id":"https://openalex.org/S4306400662","display_name":"Research Explorer (The University of Manchester)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/I28407311","host_organization_name":"University of Manchester","host_organization_lineage":["https://openalex.org/I28407311"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Barr, D R W & Dudek, P 2009, 'APRON: A cellular processor array simulation and hardware design tool', Eurasip Journal on Advances in Signal Processing, vol. 2009, 751687. https://doi.org/10.1155/2009/751687","raw_type":"info:eu-repo/semantics/article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.332.9294","doi":null,"is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.332.9294","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://personalpages.manchester.ac.uk/staff/p.dudek/papers/barr-eurasip2009.pdf","raw_type":"text"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.713.3015","doi":null,"is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.713.3015","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://personalpages.manchester.ac.uk/staff/p.dudek/papers/barr-cnna2008.pdf","raw_type":"text"},{"id":"pmh:oai:doaj.org/article:135eeb81d25344f49a6ad63ec20ad39b","doi":null,"is_oa":true,"landing_page_url":"https://doaj.org/article/135eeb81d25344f49a6ad63ec20ad39b","pdf_url":null,"source":{"id":"https://openalex.org/S4306401280","display_name":"DOAJ (DOAJ: Directory of Open Access Journals)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-sa","license_id":"https://openalex.org/licenses/cc-by-sa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"EURASIP Journal on Advances in Signal Processing, Vol 2009 (2009)","raw_type":"article"}],"best_oa_location":{"id":"doi:10.1155/2009/751687","doi":"https://doi.org/10.1155/2009/751687","is_oa":true,"landing_page_url":"https://doi.org/10.1155/2009/751687","pdf_url":"https://asp-eurasipjournals.springeropen.com/counter/pdf/10.1155/2009/751687","source":{"id":"https://openalex.org/S35920007","display_name":"EURASIP Journal on Advances in Signal Processing","issn_l":"1110-8657","issn":["1110-8657","1687-0433","1687-6172","1687-6180"],"is_oa":true,"is_in_doaj":true,"is_core":true,"listed_in":["anvur-scientific","cwts-core","doaj","dongbi-c","ki-jl-1","norway-1","poland-70","russia-white-list-2"],"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"EURASIP Journal on Advances in Signal Processing","raw_type":"journal-article"},"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320334627","display_name":"Engineering and Physical Sciences Research Council","ror":"https://ror.org/0439y7842"}],"has_content":{"grobid_xml":true,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2017170122.pdf","grobid_xml":"https://content.openalex.org/works/W2017170122.grobid-xml"},"referenced_works_count":24,"referenced_works":["https://openalex.org/W584747070","https://openalex.org/W1528002684","https://openalex.org/W1570659056","https://openalex.org/W1944616225","https://openalex.org/W2037915256","https://openalex.org/W2056717940","https://openalex.org/W2059158519","https://openalex.org/W2059807497","https://openalex.org/W2102928154","https://openalex.org/W2107025852","https://openalex.org/W2117148079","https://openalex.org/W2119241866","https://openalex.org/W2126769740","https://openalex.org/W2141000451","https://openalex.org/W2143738350","https://openalex.org/W2153245883","https://openalex.org/W2158365276","https://openalex.org/W2160841978","https://openalex.org/W2164653071","https://openalex.org/W2165342467","https://openalex.org/W2169150396","https://openalex.org/W2292809880","https://openalex.org/W3139639180","https://openalex.org/W3140062895"],"related_works":["https://openalex.org/W7097588438","https://openalex.org/W2126769740","https://openalex.org/W2026131169","https://openalex.org/W2060346092","https://openalex.org/W2066047870","https://openalex.org/W2071593711","https://openalex.org/W1522772859","https://openalex.org/W2460163562","https://openalex.org/W2121881795","https://openalex.org/W2102928154"],"abstract_inverted_index":{"We":[0,77],"present":[1,78],"a":[2,47,53,107],"software":[3,15,45,83],"environment":[4,114],"for":[5,25,62,81,115,127],"the":[6,58,63,72,82],"efficient":[7],"simulation":[8],"of":[9,65,74],"cellular":[10],"processor":[11,29,39,67,84],"arrays":[12],"(CPAs).":[13],"This":[14],"(APRON)":[16],"is":[17],"used":[18,105],"to":[19,56,95,124],"explore":[20],"algorithms":[21,126],"that":[22],"are":[23],"designed":[24],"massively":[26],"parallel":[27],"fine-grained":[28],"arrays,":[30,40],"topographic":[31],"multilayer":[32],"neural":[33],"networks,":[34],"vision":[35],"chips":[36],"with":[37,52,60],"SIMD":[38],"and":[41,71,102,112],"related":[42],"architectures.":[43],"The":[44],"uses":[46],"highly":[48],"optimised":[49],"core":[50],"combined":[51],"flexible":[54],"compiler":[55],"provide":[57],"user":[59,110],"tools":[61],"design":[64],"new":[66,116],"array":[68,85],"hardware":[69,99],"architectures":[70],"emulation":[73],"existing":[75,118],"devices.":[76],"performance":[79],"benchmarks":[80],"implemented":[86],"on":[87],"standard":[88],"commodity":[89],"microprocessors.":[90],"APRON":[91],"can":[92,103],"be":[93,104],"configured":[94],"use":[96],"additional":[97],"processing":[98],"if":[100],"necessary":[101],"as":[106],"complete":[108],"graphical":[109],"interface":[111],"development":[113],"or":[117],"CPA":[119,128],"systems,":[120],"allowing":[121],"more":[122],"users":[123],"develop":[125],"systems.":[129]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":5},{"year":2012,"cited_by_count":5}],"updated_date":"2026-11-04T10:54:05.112534","created_date":"2016-06-24T00:00:00"}