{"id":"https://openalex.org/W2016808129","doi":"https://doi.org/10.5555/2755753.2757062","title":"Accelerating arithmetic kernels with coherent attached FPGA coprocessors","display_name":"Accelerating arithmetic kernels with coherent attached FPGA coprocessors","publication_year":2015,"publication_date":"2015-03-09","ids":{"openalex":"https://openalex.org/W2016808129","doi":"https://doi.org/10.5555/2755753.2757062","mag":"2016808129"},"language":"en","primary_location":{"id":"mag:2016808129","doi":"https://doi.org/10.5555/2755753.2757062","is_oa":false,"landing_page_url":"http://dblp.uni-trier.de/db/conf/date/date2015.html#GiefersPH15","pdf_url":null,"source":{"id":"https://openalex.org/S4306418181","display_name":"Design, Automation, and Test in Europe","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":"Design, Automation, and Test in Europe","raw_type":null},"volume":null,"type":"article","indexed_in":[],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5036729583","display_name":"Heiner Giefers","orcid":"https://orcid.org/0000-0002-5811-6386","observed_orcids":["https://orcid.org/0000-0002-5811-6386"]},"institutions":[{"id":"https://openalex.org/I4210126328","display_name":"IBM Research - Zurich","ror":"https://ror.org/02js37d36","country_code":"CH","type":"facility","lineage":["https://openalex.org/I1341412227","https://openalex.org/I4210114115","https://openalex.org/I4210126328"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Heiner Giefers","raw_affiliation_strings":["IBM Research-Zurich,#TAB#"],"raw_orcid":"https://orcid.org/0000-0002-5811-6386","affiliations":[{"raw_affiliation_string":"IBM Research-Zurich,#TAB#","institution_ids":["https://openalex.org/I4210126328"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5026275592","display_name":"Raphael Polig","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I4210126328","display_name":"IBM Research - Zurich","ror":"https://ror.org/02js37d36","country_code":"CH","type":"facility","lineage":["https://openalex.org/I1341412227","https://openalex.org/I4210114115","https://openalex.org/I4210126328"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Raphael Polig","raw_affiliation_strings":["IBM Research-Zurich,#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IBM Research-Zurich,#TAB#","institution_ids":["https://openalex.org/I4210126328"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5001983294","display_name":"Christoph Hagleitner","orcid":"https://orcid.org/0000-0002-6815-7835","observed_orcids":["https://orcid.org/0000-0002-6815-7835"]},"institutions":[{"id":"https://openalex.org/I4210126328","display_name":"IBM Research - Zurich","ror":"https://ror.org/02js37d36","country_code":"CH","type":"facility","lineage":["https://openalex.org/I1341412227","https://openalex.org/I4210114115","https://openalex.org/I4210126328"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Christoph Hagleitner","raw_affiliation_strings":["IBM Research-Zurich,#TAB#"],"raw_orcid":"https://orcid.org/0000-0002-6815-7835","affiliations":[{"raw_affiliation_string":"IBM Research-Zurich,#TAB#","institution_ids":["https://openalex.org/I4210126328"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I4210126328"],"apc_list":null,"apc_paid":null,"fwci":5.5025,"has_fulltext":false,"cited_by_count":19,"citation_normalized_percentile":{"value":0.95171263,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"1072","last_page":"1077"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9976000189781189,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9976000189781189,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.0010000000474974513,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12941","display_name":"Embedded Systems and FPGA Design","score":0.00019999999494757503,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/fpga-coprocessor","display_name":"FPGA coprocessor","score":0.9300000071525574},{"id":"https://openalex.org/keywords/fft-acceleration","display_name":"FFT acceleration","score":0.6370000243186951},{"id":"https://openalex.org/keywords/energy-efficiency","display_name":"energy efficiency","score":0.7549999952316284},{"id":"https://openalex.org/keywords/shared-memory","display_name":"shared memory","score":0.609000027179718},{"id":"https://openalex.org/keywords/heterogeneous-computing","display_name":"heterogeneous computing","score":0.6439999938011169},{"id":"https://openalex.org/keywords/opencl","display_name":"OpenCL","score":0.902999997138977},{"id":"https://openalex.org/keywords/hardware-acceleration","display_name":"hardware acceleration","score":0.574999988079071},{"id":"https://openalex.org/keywords/latency","display_name":"latency","score":0.4269999861717224}],"concepts":[{"id":"https://openalex.org/C86111242","wikidata":"https://www.wikidata.org/wiki/Q859595","display_name":"Coprocessor","level":2,"score":0.9328078031539917},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8079328536987305},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5932645797729492},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5600811243057251},{"id":"https://openalex.org/C13164978","wikidata":"https://www.wikidata.org/wiki/Q600158","display_name":"Hardware acceleration","level":3,"score":0.5310488343238831},{"id":"https://openalex.org/C2742236","wikidata":"https://www.wikidata.org/wiki/Q924713","display_name":"Efficient energy use","level":2,"score":0.5123275518417358},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5002913475036621},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.48737412691116333},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.45921018719673157},{"id":"https://openalex.org/C75172450","wikidata":"https://www.wikidata.org/wiki/Q623950","display_name":"Fast Fourier transform","level":2,"score":0.446110337972641},{"id":"https://openalex.org/C49154492","wikidata":"https://www.wikidata.org/wiki/Q5300","display_name":"Central processing unit","level":2,"score":0.41820886731147766},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3546316623687744},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.26291388273239136},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"mag:2016808129","doi":"https://doi.org/10.5555/2755753.2757062","is_oa":false,"landing_page_url":"http://dblp.uni-trier.de/db/conf/date/date2015.html#GiefersPH15","pdf_url":null,"source":{"id":"https://openalex.org/S4306418181","display_name":"Design, Automation, and Test in Europe","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":"Design, Automation, and Test in Europe","raw_type":null}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5378999710083008,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"study_designs":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W595895948","https://openalex.org/W2022020111","https://openalex.org/W2024381286","https://openalex.org/W2046938074","https://openalex.org/W2059117794","https://openalex.org/W2061171222","https://openalex.org/W2133156997","https://openalex.org/W2154991996","https://openalex.org/W2159844683","https://openalex.org/W3102648408"],"related_works":["https://openalex.org/W2175524238","https://openalex.org/W2059117794","https://openalex.org/W1594582683","https://openalex.org/W1997113918","https://openalex.org/W2897878462","https://openalex.org/W2082956176","https://openalex.org/W2789687162","https://openalex.org/W2010763423","https://openalex.org/W1927160486","https://openalex.org/W2786263629"],"abstract_inverted_index":{"The":[0],"energy":[1,64,118],"efficiency":[2,119],"of":[3,109,146,165],"computer":[4],"systems":[5],"can":[6,39],"be":[7],"increased":[8],"by":[9,137],"migrating":[10],"computational":[11],"kernels":[12],"that":[13,31,97,143],"are":[14],"known":[15],"to":[16,20,27,62,90,121],"under-utilize":[17],"the":[18,42,48,84,98,144],"CPU":[19,131],"an":[21,77,122],"FPGA":[22,81],"based":[23,105],"coprocessor.":[24],"In":[25,72],"contrast":[26],"traditional":[28],"I/O-based":[29],"coprocessors":[30],"require":[32],"explicit":[33],"data":[34],"movement,":[35],"coherently":[36],"attached":[37,82,100],"accelerators":[38,66],"operate":[40],"on":[41,80,128],"same":[43],"virtual":[44],"address":[45],"space":[46],"than":[47,139],"host":[49],"CPU.":[50],"A":[51],"shared":[52],"memory":[53],"organization":[54],"enables":[55],"widely":[56],"accepted":[57],"programming":[58,150],"models":[59],"and":[60,132,160],"helps":[61],"deploy":[63],"efficient":[65],"in":[67,107,117],"general":[68],"purpose":[69],"computing":[70],"systems.":[71,167],"this":[73],"paper":[74],"we":[75],"study":[76],"FFT":[78,126],"accelerator":[79,101],"via":[83],"Coherent":[85],"Accelerator":[86],"Processor":[87],"Interface":[88],"(CAPI)":[89],"a":[91,114,129],"POWER8":[92],"processor.":[93],"Our":[94],"results":[95],"show":[96],"coherent":[99],"outperforms":[102],"device":[103],"driver":[104],"approaches":[106],"terms":[108],"latency.":[110],"Hardware":[111],"acceleration":[112],"delivers":[113],"5\u00d7":[115],"gain":[116],"compared":[120],"optimized":[123],"parallel":[124],"software":[125],"running":[127],"12-core":[130],"improves":[133],"single":[134],"thread":[135],"performance":[136],"more":[138],"2\u00d7.":[140],"We":[141],"conclude":[142],"integration":[145],"CAPI":[147],"into":[148],"heterogeneous":[149],"frameworks":[151],"such":[152],"as":[153],"OpenCL":[154],"will":[155,161],"facilitate":[156],"latency":[157],"critical":[158],"operations":[159],"further":[162],"enhance":[163],"programmability":[164],"hybrid":[166]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":3},{"year":2019,"cited_by_count":3},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":6},{"year":2016,"cited_by_count":3}],"updated_date":"2026-10-12T09:40:04.860316","created_date":"2016-06-24T00:00:00"}
