{"id":"https://openalex.org/W2016301038","doi":"https://doi.org/10.1109/isscc.2010.5433922","title":"A 45nm resilient and adaptive microprocessor core for dynamic variation tolerance","display_name":"A 45nm resilient and adaptive microprocessor core for dynamic variation tolerance","publication_year":2010,"publication_date":"2010-02-01","ids":{"openalex":"https://openalex.org/W2016301038","doi":"https://doi.org/10.1109/isscc.2010.5433922","mag":"2016301038"},"language":"en","primary_location":{"id":"doi:10.1109/isscc.2010.5433922","doi":"https://doi.org/10.1109/isscc.2010.5433922","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc.2010.5433922","pdf_url":null,"source":{"id":"https://openalex.org/S4210210374","display_name":"Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference","issn_l":"0193-6530","issn":["0193-6530","2376-8606"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core","norway-1"],"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","raw_type":"proceedings-article"},"volume":null,"type":"conference-paper","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5067753561","display_name":"James W. Tschanz","orcid":"https://orcid.org/0000-0003-0317-4332","observed_orcids":["https://orcid.org/0000-0003-0317-4332"]},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"James Tschanz","raw_affiliation_strings":["Intel, Hillsboro, OR","[Intel, Hillsboro, OR, USA]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"[Intel, Hillsboro, OR, USA]","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5014850579","display_name":"Keith A. Bowman","orcid":"https://orcid.org/0000-0002-7638-9783","observed_orcids":["https://orcid.org/0000-0002-7638-9783"]},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Keith Bowman","raw_affiliation_strings":["Intel, Hillsboro, OR","[Intel, Hillsboro, OR, USA]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"[Intel, Hillsboro, OR, USA]","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5113824454","display_name":"Shih\u2010Lien Lu","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Shih-Lien Lu","raw_affiliation_strings":["Intel, Hillsboro, OR","[Intel, Hillsboro, OR, USA]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"[Intel, Hillsboro, OR, USA]","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5043332479","display_name":"Paolo A. Aseron","orcid":"https://orcid.org/0009-0008-5013-1144","observed_orcids":["https://orcid.org/0009-0008-5013-1144"]},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Paolo Aseron","raw_affiliation_strings":["Intel, Hillsboro, OR","[Intel, Hillsboro, OR, USA]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"[Intel, Hillsboro, OR, USA]","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5036997390","display_name":"Muhammad M. Khellah","orcid":"https://orcid.org/0000-0001-9651-5639","observed_orcids":["https://orcid.org/0000-0001-9651-5639"]},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Muhammad Khellah","raw_affiliation_strings":["Intel, Hillsboro, OR","[Intel, Hillsboro, OR, USA]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"[Intel, Hillsboro, OR, USA]","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5091408102","display_name":"Arijit Raychowdhury","orcid":"https://orcid.org/0000-0001-8391-0576","observed_orcids":["https://orcid.org/0000-0001-8391-0576"]},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Arijit Raychowdhury","raw_affiliation_strings":["Intel, Hillsboro, OR","[Intel, Hillsboro, OR, USA]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"[Intel, Hillsboro, OR, USA]","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5065471436","display_name":"Bibiche M. Geuskens","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Bibiche Geuskens","raw_affiliation_strings":["Intel, Hillsboro, OR","[Intel, Hillsboro, OR, USA]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"[Intel, Hillsboro, OR, USA]","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5112838079","display_name":"Carlos Tokunaga","orcid":"https://orcid.org/0009-0002-6177-0327","observed_orcids":["https://orcid.org/0009-0002-6177-0327"]},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Carlos Tokunaga","raw_affiliation_strings":["Intel, Hillsboro, OR","[Intel, Hillsboro, OR, USA]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"[Intel, Hillsboro, OR, USA]","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5044002903","display_name":"Chris B. Wilkerson","orcid":"https://orcid.org/0009-0008-8657-2478","observed_orcids":["https://orcid.org/0009-0008-8657-2478"]},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Chris Wilkerson","raw_affiliation_strings":["Intel, Hillsboro, OR","[Intel, Hillsboro, OR, USA]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"[Intel, Hillsboro, OR, USA]","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5016416631","display_name":"Tanay Karnik","orcid":"https://orcid.org/0000-0003-0072-1492","observed_orcids":["https://orcid.org/0000-0003-0072-1492"]},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Tanay Karnik","raw_affiliation_strings":["Intel, Hillsboro, OR","[Intel, Hillsboro, OR, USA]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"[Intel, Hillsboro, OR, USA]","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5076642880","display_name":"Vivek K. De","orcid":"https://orcid.org/0000-0001-5207-1079","observed_orcids":["https://orcid.org/0000-0001-5207-1079"]},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Vivek De","raw_affiliation_strings":["Intel, Hillsboro, OR","[Intel, Hillsboro, OR, USA]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"[Intel, Hillsboro, OR, USA]","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":11.5503,"has_fulltext":false,"cited_by_count":65,"citation_normalized_percentile":{"value":0.99234284,"is_in_top_1_percent":true,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":88,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"282","last_page":"283"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.7846999764442444,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.7846999764442444,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.20890000462532043,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.00139999995008111,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dynamic-variation","display_name":"dynamic variation","score":0.6460000276565552},{"id":"https://openalex.org/keywords/microprocessor-cores","display_name":"microprocessor cores","score":0.6940000057220459},{"id":"https://openalex.org/keywords/error-detection","display_name":"error detection","score":0.6399999856948853},{"id":"https://openalex.org/keywords/error-recovery","display_name":"error recovery","score":0.7480000257492065},{"id":"https://openalex.org/keywords/frequency-adaptation","display_name":"frequency adaptation","score":0.6140000224113464},{"id":"https://openalex.org/keywords/low-voltage-operation","display_name":"low-voltage operation","score":0.7419999837875366},{"id":"https://openalex.org/keywords/45-nm-cmos","display_name":"45 nm CMOS","score":0.7630000114440918},{"id":"https://openalex.org/keywords/throughput-optimization","display_name":"throughput maximization","score":0.31200000643730164},{"id":"https://openalex.org/keywords/process-variation-tolerance","display_name":"process variation tolerance","score":0.4099999964237213}],"concepts":[{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.8232032060623169},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.6802788376808167},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.6689750552177429},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.653823733329773},{"id":"https://openalex.org/C2775937380","wikidata":"https://www.wikidata.org/wiki/Q1232589","display_name":"Replica","level":2,"score":0.5567377805709839},{"id":"https://openalex.org/C103088060","wikidata":"https://www.wikidata.org/wiki/Q1062839","display_name":"Error detection and correction","level":2,"score":0.5331933498382568},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.43921008706092834},{"id":"https://openalex.org/C2164484","wikidata":"https://www.wikidata.org/wiki/Q5170150","display_name":"Core (optical fiber)","level":2,"score":0.4339011311531067},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.405510812997818},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.299805223941803},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.19520065188407898},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.17218393087387085},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.15621721744537354},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.13707312941551208},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.10835874080657959},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isscc.2010.5433922","doi":"https://doi.org/10.1109/isscc.2010.5433922","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc.2010.5433922","pdf_url":null,"source":{"id":"https://openalex.org/S4210210374","display_name":"Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference","issn_l":"0193-6530","issn":["0193-6530","2376-8606"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core","norway-1"],"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.6773999929428101}],"study_designs":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W1541483005","https://openalex.org/W1811377747","https://openalex.org/W2121618685","https://openalex.org/W2156667996","https://openalex.org/W2178304595"],"related_works":["https://openalex.org/W2015917466","https://openalex.org/W2077857987","https://openalex.org/W2110283673","https://openalex.org/W1970806136","https://openalex.org/W3139751470","https://openalex.org/W2130127169","https://openalex.org/W1986949140","https://openalex.org/W55808171","https://openalex.org/W1987474522","https://openalex.org/W1993986066"],"abstract_inverted_index":{"A":[0],"45":[1],"nm":[2],"1.3":[3],"GHz":[4],"microprocessor":[5],"core":[6],"employs":[7],"error-detection":[8],"circuits,":[9,12,15],"tunable":[10],"replica":[11],"and":[13,55],"error-recovery":[14],"to":[16,35,50,57],"mitigate":[17],"dynamic":[18],"variation":[19],"guardbands":[20],"for":[21],"maximum":[22],"throughput.":[23],"An":[24],"adaptive":[25],"clock":[26],"controller":[27],"adjusts":[28],"the":[29],"frequency":[30],"based":[31],"on":[32],"error":[33],"statistics":[34],"optimize":[36],"efficiency.":[37],"Silicon":[38],"measurements":[39],"show":[40],"resilient":[41],"operation":[42],"as":[43,45],"well":[44],"throughput":[46],"gains":[47],"of":[48],"12":[49],"16%":[51],"at":[52,59],"1.0":[53],"V":[54],"22":[56],"23%":[58],"0.8":[60],"V.":[61]},"counts_by_year":[{"year":2023,"cited_by_count":2},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":3},{"year":2018,"cited_by_count":4},{"year":2017,"cited_by_count":6},{"year":2016,"cited_by_count":7},{"year":2015,"cited_by_count":4},{"year":2014,"cited_by_count":11},{"year":2013,"cited_by_count":6},{"year":2012,"cited_by_count":5}],"updated_date":"2026-11-07T11:25:07.637180","created_date":"2016-06-24T00:00:00"}