{"id":"https://openalex.org/W2015395294","doi":"https://doi.org/10.1109/mm.2014.14","title":"Efficient Spatial Processing Element Control via Triggered Instructions","display_name":"Efficient Spatial Processing Element Control via Triggered Instructions","publication_year":2014,"publication_date":"2014-03-10","ids":{"openalex":"https://openalex.org/W2015395294","doi":"https://doi.org/10.1109/mm.2014.14","mag":"2015395294"},"language":"en","primary_location":{"id":"doi:10.1109/mm.2014.14","doi":"https://doi.org/10.1109/mm.2014.14","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mm.2014.14","pdf_url":null,"source":{"id":"https://openalex.org/S59697426","display_name":"IEEE Micro","issn_l":"0272-1732","issn":["0272-1732","1937-4143"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core","dongbi-a","jufo-3","norway-2","poland-140","russia-white-list-1"],"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Micro","raw_type":"journal-article"},"volume":null,"type":"article","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5024901904","display_name":"Angshuman Parashar","orcid":"https://orcid.org/0000-0001-9936-6501","observed_orcids":["https://orcid.org/0000-0001-9936-6501"]},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Angshuman Parashar","raw_affiliation_strings":["Intel","Intel#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5009910914","display_name":"Michael Pellauer","orcid":"https://orcid.org/0000-0002-5305-4307","observed_orcids":["https://orcid.org/0000-0002-5305-4307"]},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Michael Pellauer","raw_affiliation_strings":["Intel","Intel#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Michael Adler","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Michael Adler","raw_affiliation_strings":["Intel","Intel#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5005443434","display_name":"Bushra Ahsan","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Bushra Ahsan","raw_affiliation_strings":["Intel","Intel#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5060189926","display_name":"Neal Clayton Crago","orcid":"https://orcid.org/0000-0001-7774-0531","observed_orcids":["https://orcid.org/0000-0001-7774-0531"]},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Neal Crago","raw_affiliation_strings":["Intel","Intel#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5078894707","display_name":"Daniel Lustig","orcid":"https://orcid.org/0000-0001-9763-7304","observed_orcids":["https://orcid.org/0000-0001-9763-7304"]},"institutions":[{"id":"https://openalex.org/I20089843","display_name":"Princeton University","ror":"https://ror.org/00hx57361","country_code":"US","type":"education","lineage":["https://openalex.org/I20089843"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Daniel Lustig","raw_affiliation_strings":["Princeton University","Princeton University#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Princeton University","institution_ids":["https://openalex.org/I20089843"]},{"raw_affiliation_string":"Princeton University#TAB#","institution_ids":["https://openalex.org/I20089843"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Vladimir Pavlov","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Vladimir Pavlov","raw_affiliation_strings":["Intel","Intel#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5053597061","display_name":"Antonia Zhai","orcid":"https://orcid.org/0000-0002-8921-1415","observed_orcids":["https://orcid.org/0000-0002-8921-1415"]},"institutions":[{"id":"https://openalex.org/I130238516","display_name":"University of Minnesota","ror":"https://ror.org/017zqws13","country_code":"US","type":"education","lineage":["https://openalex.org/I130238516"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Antonia Zhai","raw_affiliation_strings":["University of Minnesota"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Minnesota","institution_ids":["https://openalex.org/I130238516"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5075681742","display_name":"Mohit Gambhir","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Mohit Gambhir","raw_affiliation_strings":["Intel","Intel#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5078825915","display_name":"Aamer Jaleel","orcid":"https://orcid.org/0000-0002-5709-2992","observed_orcids":["https://orcid.org/0000-0002-5709-2992"]},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Aamer Jaleel","raw_affiliation_strings":["Intel","Intel#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5042818004","display_name":"R. Allmon","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Randy Allmon","raw_affiliation_strings":["Intel","Intel#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5009749854","display_name":"Rachid Rayess","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Rachid Rayess","raw_affiliation_strings":["Intel","Intel#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5082025700","display_name":"Stephen Maresh","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Stephen Maresh","raw_affiliation_strings":["Intel","Intel#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5024384625","display_name":"Joel Emer","orcid":"https://orcid.org/0000-0002-3459-5466","observed_orcids":["https://orcid.org/0000-0002-3459-5466"]},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Joel Emer","raw_affiliation_strings":["Intel","Intel#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":{"value":2995,"currency":"USD","value_usd":2995},"apc_paid":null,"fwci":2.5619,"has_fulltext":false,"cited_by_count":18,"citation_normalized_percentile":{"value":0.89113052,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":87,"max":98},"biblio":{"volume":"34","issue":"3","first_page":"120","last_page":"137"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9961000084877014,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9961000084877014,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.002199999988079071,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.00039999998989515007,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/processing-element-array","display_name":"processing element array","score":0.7940000295639038},{"id":"https://openalex.org/keywords/spatial-parallelism","display_name":"spatial parallelism","score":0.9739999771118164},{"id":"https://openalex.org/keywords/branch-elimination","display_name":"branch elimination","score":0.5350000262260437},{"id":"https://openalex.org/keywords/multithreading","display_name":"multithreading","score":0.9300000071525574}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.9216957092285156},{"id":"https://openalex.org/C201410400","wikidata":"https://www.wikidata.org/wiki/Q1064412","display_name":"Multithreading","level":3,"score":0.7380789518356323},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.5380498766899109},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5104695558547974},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.49202439188957214},{"id":"https://openalex.org/C2781172179","wikidata":"https://www.wikidata.org/wiki/Q853109","display_name":"Parallelism (grammar)","level":2,"score":0.45533862709999084},{"id":"https://openalex.org/C106515295","wikidata":"https://www.wikidata.org/wiki/Q26806595","display_name":"Parallel processing","level":2,"score":0.44050827622413635},{"id":"https://openalex.org/C2775924081","wikidata":"https://www.wikidata.org/wiki/Q55608371","display_name":"Control (management)","level":2,"score":0.4320872724056244},{"id":"https://openalex.org/C140763907","wikidata":"https://www.wikidata.org/wiki/Q2714055","display_name":"Instruction-level parallelism","level":3,"score":0.42694494128227234},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.41986629366874695},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.3838799297809601},{"id":"https://openalex.org/C138101251","wikidata":"https://www.wikidata.org/wiki/Q213092","display_name":"Thread (computing)","level":2,"score":0.22198334336280823},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.2182217836380005},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.10503321886062622},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mm.2014.14","doi":"https://doi.org/10.1109/mm.2014.14","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mm.2014.14","pdf_url":null,"source":{"id":"https://openalex.org/S59697426","display_name":"IEEE Micro","issn_l":"0272-1732","issn":["0272-1732","1937-4143"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core","dongbi-a","jufo-3","norway-2","poland-140","russia-white-list-1"],"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Micro","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":27,"referenced_works":["https://openalex.org/W105298322","https://openalex.org/W326353637","https://openalex.org/W1506687165","https://openalex.org/W2005345974","https://openalex.org/W2017086619","https://openalex.org/W2049558311","https://openalex.org/W2056999868","https://openalex.org/W2066210260","https://openalex.org/W2074812550","https://openalex.org/W2097117297","https://openalex.org/W2107923684","https://openalex.org/W2115611348","https://openalex.org/W2121082877","https://openalex.org/W2122992089","https://openalex.org/W2130408605","https://openalex.org/W2142501475","https://openalex.org/W2147345262","https://openalex.org/W2157118812","https://openalex.org/W2164939754","https://openalex.org/W2165099691","https://openalex.org/W2171532807","https://openalex.org/W2172212694","https://openalex.org/W2295946175","https://openalex.org/W3143533263","https://openalex.org/W4231369534","https://openalex.org/W4239997146","https://openalex.org/W6680290872"],"related_works":["https://openalex.org/W2074812550","https://openalex.org/W1988150112","https://openalex.org/W2763025241","https://openalex.org/W2625517949","https://openalex.org/W2795408871","https://openalex.org/W2416993663","https://openalex.org/W2055469530","https://openalex.org/W2114907104","https://openalex.org/W4383604851","https://openalex.org/W2128194410"],"abstract_inverted_index":{"In":[0],"this":[1],"article,":[2],"the":[3,27,63],"authors":[4],"present":[5],"triggered":[6],"instructions,":[7],"a":[8,54,81],"novel":[9],"control":[10],"paradigm":[11],"for":[12],"arrays":[13],"of":[14,65],"processing":[15],"elements":[16],"(PEs)":[17],"aimed":[18],"at":[19],"exploiting":[20],"spatial":[21],"parallelism.":[22],"Triggered":[23],"instructions":[24],"completely":[25],"eliminate":[26],"program":[28],"counter":[29],"and":[30,72],"allow":[31,44],"programs":[32],"to":[33,47,57],"transition":[34],"concisely":[35],"between":[36],"states":[37],"without":[38],"explicit":[39],"branch":[40],"instructions.":[41],"They":[42],"also":[43],"efficient":[45],"reactivity":[46],"inter-PE":[48],"communication":[49],"traffic.":[50],"The":[51],"approach":[52],"provides":[53],"unified":[55],"mechanism":[56],"avoid":[58],"overserialized":[59],"execution,":[60],"essentially":[61],"achieving":[62],"effect":[64],"techniques":[66],"such":[67],"as":[68],"dynamic":[69],"instruction":[70],"reordering":[71],"multithreading,":[73],"which":[74],"each":[75],"require":[76],"distinct":[77],"hardware":[78],"mechanisms":[79],"in":[80],"traditional":[82],"sequential":[83],"architecture.":[84]},"counts_by_year":[{"year":2025,"cited_by_count":3},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2020,"cited_by_count":4},{"year":2017,"cited_by_count":1},{"year":2015,"cited_by_count":6}],"updated_date":"2026-11-12T12:28:57.059296","created_date":"2016-06-24T00:00:00"}
