{"id":"https://openalex.org/W2006097283","doi":null,"title":"Principles of CMOS VLSI Design: A Systems Perspective","display_name":"Principles of CMOS VLSI Design: A Systems Perspective","publication_year":1985,"publication_date":"1985-01-01","ids":{"openalex":"https://openalex.org/W2006097283","mag":"2006097283"},"language":"en","primary_location":{"id":"pmh:oai:cds.cern.ch:113244","doi":null,"is_oa":false,"landing_page_url":"http://cds.cern.ch/record/113244","pdf_url":null,"source":{"id":"https://openalex.org/S4306402195","display_name":"CERN Document Server (European Organization for Nuclear Research)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/I67311998","host_organization_name":"European Organization for Nuclear Research","host_organization_lineage":["https://openalex.org/I67311998"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":null},"volume":null,"type":"article","indexed_in":[],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5001267886","display_name":"Neil H. E. Weste","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I1283103587","display_name":"AT&T (United States)","ror":"https://ror.org/02bbd5539","country_code":"US","type":"company","lineage":["https://openalex.org/I1283103587"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Neil Weste","raw_affiliation_strings":["AT&T Bell Labs.#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"AT&T Bell Labs.#TAB#","institution_ids":["https://openalex.org/I1283103587"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5011814002","display_name":"Kamran Eshraghian","orcid":"https://orcid.org/0009-0007-5372-8010","observed_orcids":["https://orcid.org/0009-0007-5372-8010"]},"institutions":[{"id":"https://openalex.org/I5681781","display_name":"The University of Adelaide","ror":"https://ror.org/00892tw58","country_code":"AU","type":"education","lineage":["https://openalex.org/I4405259444","https://openalex.org/I5681781"]}],"countries":["AU"],"is_corresponding":false,"raw_author_name":"Kamran Eshraghian","raw_affiliation_strings":["*University of Adelaide"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"*University of Adelaide","institution_ids":["https://openalex.org/I5681781"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":14.5416,"has_fulltext":false,"cited_by_count":1566,"citation_normalized_percentile":{"value":0.99407901,"is_in_top_1_percent":true,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":96,"max":100},"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.5371000170707703,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.5371000170707703,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.3970000147819519,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.049400001764297485,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cmos-vlsi-design","display_name":"CMOS VLSI design","score":0.9010000228881836},{"id":"https://openalex.org/keywords/mos-transistors","display_name":"MOS transistors","score":0.9330000281333923},{"id":"https://openalex.org/keywords/cmos-logic","display_name":"CMOS logic","score":0.8309999704360962},{"id":"https://openalex.org/keywords/cmos-inverter","display_name":"CMOS inverter","score":0.8489999771118164},{"id":"https://openalex.org/keywords/transmission-gate","display_name":"transmission gate","score":0.9490000009536743},{"id":"https://openalex.org/keywords/bipolar-devices","display_name":"bipolar devices","score":0.8930000066757202},{"id":"https://openalex.org/keywords/circuit-characterization","display_name":"circuit characterization","score":0.6309999823570251},{"id":"https://openalex.org/keywords/power-consumption","display_name":"power consumption","score":0.7360000014305115},{"id":"https://openalex.org/keywords/transistor-sizing","display_name":"transistor sizing","score":0.8059999942779541},{"id":"https://openalex.org/keywords/charge-sharing","display_name":"charge sharing","score":0.7630000114440918},{"id":"https://openalex.org/keywords/yield","display_name":"yield","score":0.6899999976158142},{"id":"https://openalex.org/keywords/cmos-logic-gates","display_name":"CMOS logic gates","score":0.7170000076293945},{"id":"https://openalex.org/keywords/design-for-testability","display_name":"design for testability","score":0.8349999785423279},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"automatic test pattern generation","score":0.9380000233650208},{"id":"https://openalex.org/keywords/design-for-manufacturing","display_name":"design for manufacturing","score":0.9890000224113464},{"id":"https://openalex.org/keywords/adders","display_name":"adders","score":0.6769999861717224},{"id":"https://openalex.org/keywords/binary-counter","display_name":"binary counter","score":0.7289999723434448},{"id":"https://openalex.org/keywords/multipliers","display_name":"multipliers","score":0.9449999928474426},{"id":"https://openalex.org/keywords/memory","display_name":"memory","score":0.6159999966621399},{"id":"https://openalex.org/keywords/finite-state-machines","display_name":"finite automata","score":0.9919999837875366},{"id":"https://openalex.org/keywords/programmable-logic-arrays","display_name":"programmable logic arrays","score":0.9309999942779541}],"concepts":[{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.7386254668235779},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.6228330731391907},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.5265693664550781},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.48640871047973633},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.46560317277908325},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.4161917269229889},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4045619070529938},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.37817245721817017},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.3054807782173157},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.2958037257194519},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.26616594195365906}],"mesh":[],"locations_count":4,"locations":[{"id":"pmh:oai:cds.cern.ch:113244","doi":null,"is_oa":false,"landing_page_url":"http://cds.cern.ch/record/113244","pdf_url":null,"source":{"id":"https://openalex.org/S4306402195","display_name":"CERN Document Server (European Organization for Nuclear Research)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/I67311998","host_organization_name":"European Organization for Nuclear Research","host_organization_lineage":["https://openalex.org/I67311998"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":null},{"id":"pmh:oai:cds.cern.ch:245825","doi":null,"is_oa":false,"landing_page_url":"http://cds.cern.ch/record/245825","pdf_url":null,"source":{"id":"https://openalex.org/S4306402195","display_name":"CERN Document Server (European Organization for Nuclear Research)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/I67311998","host_organization_name":"European Organization for Nuclear Research","host_organization_lineage":["https://openalex.org/I67311998"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":null},{"id":"pmh:oai:katalog.pustaka.unand.ac.id:slims-7693","doi":null,"is_oa":false,"landing_page_url":"http://katalog.pustaka.unand.ac.id//index.php?p=show_detail&amp;id=7693","pdf_url":null,"source":{"id":"https://openalex.org/S4377196922","display_name":"Andalas University Repository (Andalas University)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/I55892964","host_organization_name":"Andalas University","host_organization_lineage":["https://openalex.org/I55892964"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":null},{"id":"mag:2006097283","doi":null,"is_oa":false,"landing_page_url":"http://cds.cern.ch/record/245825","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":null,"raw_source_name":null,"raw_type":null}],"best_oa_location":null,"sustainable_development_goals":[],"sustainable_development_goals_aurora":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.5799999833106995}],"study_designs":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W3103339143","https://openalex.org/W1666015432","https://openalex.org/W1633471522","https://openalex.org/W2071693325","https://openalex.org/W1555915743","https://openalex.org/W2141849037","https://openalex.org/W1554885925","https://openalex.org/W2135955108","https://openalex.org/W1556480701","https://openalex.org/W2170191597","https://openalex.org/W1578458555","https://openalex.org/W1539883310","https://openalex.org/W2162211138","https://openalex.org/W2079170559","https://openalex.org/W1984588379","https://openalex.org/W1598341975","https://openalex.org/W1555253106","https://openalex.org/W2134067926","https://openalex.org/W2147970500","https://openalex.org/W1587217691"],"abstract_inverted_index":{"Introduction":[0],"to":[1],"CMOS":[2,10,14,26,30,40,48,68,88,94,125,135,151],"Circuits.":[3],"Introduction.":[4,19,60,93,118,138,154],"MOS":[5,7,16,20,85],"Transistors.":[6],"Transistor":[8,17,70,86],"Switches.":[9],"Logic.":[11,183],"Circuit":[12,55,89],"Representations.":[13],"Summary.":[15],"Theory.":[18],"Device":[21],"Design":[22,51,80,99,109,116,119,121,123,127,129,132,141,148],"Equation.":[23],"The":[24,32,35],"Complemenatry":[25],"Inverter-DC":[27],"Characteristics.":[28,67],"Alternate":[29],"Inverters.":[31],"Differential":[33],"Stage.":[34],"Transmission":[36],"Gate.":[37],"Bipolar":[38],"Devices.":[39],"Processing":[41],"Technology.":[42],"Silicon":[43],"Semiconductor":[44],"Technology:":[45],"An":[46],"Overview.":[47],"Technologies.":[49],"Layout":[50],"Rules.":[52],"CAD":[53],"Issues.":[54],"Characterization":[56],"and":[57,90,107,156,162,167,172],"Performance":[58],"Estimation.":[59,62,64],"Resistance":[61],"Capacitance":[63],"Inductance.":[65],"Switching":[66],"Gate":[69],"Sizing.":[71],"Power":[72],"Consumption.":[73],"Determination":[74],"of":[75,84,100,110],"Conductor":[76],"Size.":[77],"Charge":[78],"Sharing.":[79],"Margining.":[81],"Yield.":[82],"Scaling":[83],"Dimensions.":[87],"Logic":[91,95,102,111,179],"Design.":[92,153],"Structures.":[96,114,164],"Basic":[97],"Physical":[98,106],"Simple":[101],"Gates.":[103,112],"Clocking":[104],"Strategies.":[105,117,122],"Electrical":[108],"10":[113],"Structured":[115],"Economics.":[120],"Methods.":[124],"Chip":[126],"Options.":[128],"Capture":[130],"Tools.":[131,134],"Verification":[133],"Test":[136,145],"Methodolgies.":[137],"Fault":[139],"Models.":[140],"for":[142,149],"Testability.":[143],"Automatic":[144],"Pattern":[146],"Generation.":[147],"Manufacturability.":[150],"Subsystem":[152],"Adders":[155],"Related":[157],"Functions.":[158],"Binary":[159],"Counters.":[160],"Multipliers":[161],"Filter":[163],"Random":[165,181],"Access":[166],"Serial":[168],"Memory.":[169],"Datapaths.":[170],"FIR":[171],"IIR":[173],"Filters.":[174],"Finite":[175],"State":[176],"Machines.":[177],"Programmable":[178],"Arrays.":[180],"Control":[182]},"counts_by_year":[{"year":2025,"cited_by_count":3},{"year":2024,"cited_by_count":8},{"year":2023,"cited_by_count":18},{"year":2022,"cited_by_count":11},{"year":2021,"cited_by_count":16},{"year":2020,"cited_by_count":23},{"year":2019,"cited_by_count":19},{"year":2018,"cited_by_count":19},{"year":2017,"cited_by_count":24},{"year":2016,"cited_by_count":37},{"year":2015,"cited_by_count":33},{"year":2014,"cited_by_count":42},{"year":2013,"cited_by_count":45},{"year":2012,"cited_by_count":40}],"updated_date":"2026-10-12T09:40:04.860316","created_date":"2025-10-10T00:00:00"}
