{"id":"https://openalex.org/W2004351586","doi":"https://doi.org/10.1109/vdat.2007.373197","title":"Microprocessor Modeling and Simulation with SystemC","display_name":"Microprocessor Modeling and Simulation with SystemC","publication_year":2007,"publication_date":"2007-04-01","ids":{"openalex":"https://openalex.org/W2004351586","doi":"https://doi.org/10.1109/vdat.2007.373197","mag":"2004351586"},"language":"en","primary_location":{"id":"doi:10.1109/vdat.2007.373197","doi":"https://doi.org/10.1109/vdat.2007.373197","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vdat.2007.373197","pdf_url":null,"source":{"id":"https://openalex.org/S4306420232","display_name":"International Symposium on VLSI Design, Automation and Test","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","raw_type":"proceedings-article"},"volume":null,"type":"conference-paper","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5067198078","display_name":"Yen-Ju Lu","orcid":"https://orcid.org/0000-0001-8400-4188","observed_orcids":["https://orcid.org/0000-0001-8400-4188"]},"institutions":[{"id":"https://openalex.org/I901624438","display_name":"Realtek (Taiwan)","ror":"https://ror.org/05x1ffr83","country_code":"TW","type":"company","lineage":["https://openalex.org/I901624438"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Yen-Ju Lu","raw_affiliation_strings":["Realtek Semiconductor Corporation, Hsinchu, Taiwan","Realtek Semicond. Corp., Hsinchu"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Realtek Semiconductor Corporation, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I901624438"]},{"raw_affiliation_string":"Realtek Semicond. Corp., Hsinchu","institution_ids":["https://openalex.org/I901624438"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5053030946","display_name":"Chen-Tung Lin","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I901624438","display_name":"Realtek (Taiwan)","ror":"https://ror.org/05x1ffr83","country_code":"TW","type":"company","lineage":["https://openalex.org/I901624438"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Chen-Tung Lin","raw_affiliation_strings":["Realtek Semiconductor Corporation, Hsinchu, Taiwan","Realtek Semicond. Corp., Hsinchu"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Realtek Semiconductor Corporation, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I901624438"]},{"raw_affiliation_string":"Realtek Semicond. Corp., Hsinchu","institution_ids":["https://openalex.org/I901624438"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102066701","display_name":"Chi-Feng Wu","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I901624438","display_name":"Realtek (Taiwan)","ror":"https://ror.org/05x1ffr83","country_code":"TW","type":"company","lineage":["https://openalex.org/I901624438"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Chi-Feng Wu","raw_affiliation_strings":["Realtek Semiconductor Corporation, Hsinchu, Taiwan","Realtek Semicond. Corp., Hsinchu"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Realtek Semiconductor Corporation, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I901624438"]},{"raw_affiliation_string":"Realtek Semicond. Corp., Hsinchu","institution_ids":["https://openalex.org/I901624438"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5109863688","display_name":"Shih-Arn Hwang","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I901624438","display_name":"Realtek (Taiwan)","ror":"https://ror.org/05x1ffr83","country_code":"TW","type":"company","lineage":["https://openalex.org/I901624438"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Shih-Arn Hwang","raw_affiliation_strings":["Realtek Semiconductor Corporation, Hsinchu, Taiwan","Realtek Semicond. Corp., Hsinchu"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Realtek Semiconductor Corporation, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I901624438"]},{"raw_affiliation_string":"Realtek Semicond. Corp., Hsinchu","institution_ids":["https://openalex.org/I901624438"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101137294","display_name":"Ying-Hsi Lin","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I901624438","display_name":"Realtek (Taiwan)","ror":"https://ror.org/05x1ffr83","country_code":"TW","type":"company","lineage":["https://openalex.org/I901624438"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Ying-Hsi Lin","raw_affiliation_strings":["Realtek Semiconductor Corporation, Hsinchu, Taiwan","Realtek Semicond. Corp., Hsinchu"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Realtek Semiconductor Corporation, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I901624438"]},{"raw_affiliation_string":"Realtek Semicond. Corp., Hsinchu","institution_ids":["https://openalex.org/I901624438"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I901624438"],"apc_list":null,"apc_paid":null,"fwci":0.418,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.51860383,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":9.999999747378752e-05,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":9.999999747378752e-05,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/systemc","display_name":"SystemC","score":0.9950000047683716},{"id":"https://openalex.org/keywords/electronic-system-level-design","display_name":"electronic system level design","score":0.843999981880188},{"id":"https://openalex.org/keywords/simulation-acceleration","display_name":"simulation acceleration","score":0.6990000009536743},{"id":"https://openalex.org/keywords/levels-of-abstraction","display_name":"levels of abstraction","score":0.8640000224113464},{"id":"https://openalex.org/keywords/hardware-verification","display_name":"hardware verification","score":0.6129999756813049}],"concepts":[{"id":"https://openalex.org/C2776928060","wikidata":"https://www.wikidata.org/wiki/Q1753563","display_name":"SystemC","level":2,"score":0.9800723195075989},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7924102544784546},{"id":"https://openalex.org/C169571997","wikidata":"https://www.wikidata.org/wiki/Q966099","display_name":"Transaction-level modeling","level":3,"score":0.724793016910553},{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.6594967842102051},{"id":"https://openalex.org/C124304363","wikidata":"https://www.wikidata.org/wiki/Q673661","display_name":"Abstraction","level":2,"score":0.5868105292320251},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5585602521896362},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5230908393859863},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.5033435225486755},{"id":"https://openalex.org/C77495112","wikidata":"https://www.wikidata.org/wiki/Q5358436","display_name":"Electronic system-level design and verification","level":2,"score":0.47864070534706116},{"id":"https://openalex.org/C2992317946","wikidata":"https://www.wikidata.org/wiki/Q712144","display_name":"De facto","level":2,"score":0.46707016229629517},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.45920851826667786},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.43587902188301086},{"id":"https://openalex.org/C179603123","wikidata":"https://www.wikidata.org/wiki/Q1941921","display_name":"Modeling language","level":3,"score":0.4286194443702698},{"id":"https://openalex.org/C154488198","wikidata":"https://www.wikidata.org/wiki/Q1335007","display_name":"Embedded software","level":3,"score":0.4142322540283203},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.2487848997116089},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.14648693799972534},{"id":"https://openalex.org/C199539241","wikidata":"https://www.wikidata.org/wiki/Q7748","display_name":"Law","level":1,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C17744445","wikidata":"https://www.wikidata.org/wiki/Q36442","display_name":"Political science","level":0,"score":0.0},{"id":"https://openalex.org/C111472728","wikidata":"https://www.wikidata.org/wiki/Q9471","display_name":"Epistemology","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vdat.2007.373197","doi":"https://doi.org/10.1109/vdat.2007.373197","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vdat.2007.373197","pdf_url":null,"source":{"id":"https://openalex.org/S4306420232","display_name":"International Symposium on VLSI Design, Automation and Test","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":2,"referenced_works":["https://openalex.org/W1974234860","https://openalex.org/W2127857039"],"related_works":["https://openalex.org/W161175043","https://openalex.org/W3009904093","https://openalex.org/W2375820625","https://openalex.org/W4253308885","https://openalex.org/W7098479256","https://openalex.org/W159653609","https://openalex.org/W2113153592","https://openalex.org/W2115331097","https://openalex.org/W2130447690","https://openalex.org/W4252858011"],"abstract_inverted_index":{"Complexity":[0],"of":[1,9,22,56,65],"advanced":[2],"chip":[3],"designs":[4],"is":[5,25,59],"driving":[6],"the":[7,20,28,38,49,62,78],"progress":[8],"ESL":[10,31,57],"methodology.":[11],"SystemC,":[12],"with":[13,43],"its":[14],"mature":[15],"C++":[16],"language":[17],"environment":[18],"and":[19,48,86],"availability":[21],"public":[23],"tools,":[24],"quickly":[26],"becoming":[27],"de":[29],"facto":[30],"language.":[32],"In":[33],"this":[34],"paper,":[35],"we":[36],"demonstrate":[37],"methodology":[39,58,79],"by":[40,61],"microprocessor":[41],"modeling":[42],"systemC.":[44],"Various":[45],"abstraction":[46],"levels":[47],"corresponding":[50],"purposes":[51],"are":[52],"addressed.":[53],"The":[54],"advantage":[55],"shown":[60],"experimental":[63],"results":[64],"simulation":[66,76],"speed.":[67],"With":[68],"a":[69],"18":[70],"times":[71,75],"to":[72],"over":[73],"500":[74],"speed-up,":[77],"has":[80],"proved":[81],"useful":[82],"in":[83],"modeling,":[84],"verification,":[85],"software":[87],"development.":[88]},"counts_by_year":[{"year":2014,"cited_by_count":1},{"year":2012,"cited_by_count":2}],"updated_date":"2026-10-05T09:50:58.205359","created_date":"2016-06-24T00:00:00"}