{"id":"https://openalex.org/W2000376769","doi":"https://doi.org/10.1117/12.724042","title":"High parallel-pipeline integer-pel and fractional-pel motion estimation VLSI architectures for H.264/AVC","display_name":"High parallel-pipeline integer-pel and fractional-pel motion estimation VLSI architectures for H.264/AVC","publication_year":2007,"publication_date":"2007-05-18","ids":{"openalex":"https://openalex.org/W2000376769","doi":"https://doi.org/10.1117/12.724042","mag":"2000376769"},"language":"en","primary_location":{"id":"doi:10.1117/12.724042","doi":"https://doi.org/10.1117/12.724042","is_oa":false,"landing_page_url":"https://doi.org/10.1117/12.724042","pdf_url":null,"source":{"id":"https://openalex.org/S183492911","display_name":"Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE","issn_l":"0277-786X","issn":["0277-786X","1996-756X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core","norway-1"],"host_organization":"https://openalex.org/P4310315543","host_organization_name":"SPIE","host_organization_lineage":["https://openalex.org/P4310315543"],"host_organization_lineage_names":["SPIE"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"SPIE Proceedings","raw_type":"proceedings-article"},"volume":null,"type":"conference-paper","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5065944335","display_name":"Armando Mora Campos","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I183562009","display_name":"Instituto Tecnol\u00f3gico de Quer\u00e9taro","ror":"https://ror.org/00ca9p538","country_code":"MX","type":"education","lineage":["https://openalex.org/I183562009"]}],"countries":["MX"],"is_corresponding":false,"raw_author_name":"Armando Mora-Campos","raw_affiliation_strings":["Instituto Tecnol\u00f3gico de Quer\u00e9taro (Mexico)","Instituto Tecnologico de Quer\u00e9taro (Mexico)"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Instituto Tecnol\u00f3gico de Quer\u00e9taro (Mexico)","institution_ids":["https://openalex.org/I183562009"]},{"raw_affiliation_string":"Instituto Tecnologico de Quer\u00e9taro (Mexico)","institution_ids":["https://openalex.org/I183562009"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5049627310","display_name":"F. Ballester","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I60053951","display_name":"Universitat Polit\u00e8cnica de Val\u00e8ncia","ror":"https://ror.org/01460j859","country_code":"ES","type":"education","lineage":["https://openalex.org/I60053951"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Francisco J. Ballester-Merelo","raw_affiliation_strings":["Univ. Polit\u00e9cnica de Valencia (Spain)"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Univ. Polit\u00e9cnica de Valencia (Spain)","institution_ids":["https://openalex.org/I60053951"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5072333636","display_name":"Marcos Mart\u00ednez-Peiro","orcid":"https://orcid.org/0000-0002-3854-3735","observed_orcids":["https://orcid.org/0000-0002-3854-3735"]},"institutions":[{"id":"https://openalex.org/I60053951","display_name":"Universitat Polit\u00e8cnica de Val\u00e8ncia","ror":"https://ror.org/01460j859","country_code":"ES","type":"education","lineage":["https://openalex.org/I60053951"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Marcos A. Mart\u00ednez-Peir\u00f3","raw_affiliation_strings":["Univ. Polit\u00e9cnica de Valencia (Spain)"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Univ. Polit\u00e9cnica de Valencia (Spain)","institution_ids":["https://openalex.org/I60053951"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5012609965","display_name":"Jos\u00e9 A. Canals-Esteve","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I60053951","display_name":"Universitat Polit\u00e8cnica de Val\u00e8ncia","ror":"https://ror.org/01460j859","country_code":"ES","type":"education","lineage":["https://openalex.org/I60053951"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Jos\u00e9 A. Canals-Esteve","raw_affiliation_strings":["Univ. Polit\u00e9cnica de Valencia (Spain)"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Univ. Polit\u00e9cnica de Valencia (Spain)","institution_ids":["https://openalex.org/I60053951"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.0,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":93,"max":95},"biblio":{"volume":"6590","issue":null,"first_page":"659010","last_page":"659010"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10741","display_name":"Video Coding and Compression Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10741","display_name":"Video Coding and Compression Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10901","display_name":"Advanced Data Compression Techniques","score":0.0,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13292","display_name":"Embedded Systems and FPGA Applications","score":0.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/motion-estimation","display_name":"motion estimation","score":0.9819999933242798},{"id":"https://openalex.org/keywords/h-264","display_name":"H.264/AVC","score":0.9350000023841858},{"id":"https://openalex.org/keywords/vlsi-architecture","display_name":"VLSI architecture","score":0.8700000047683716},{"id":"https://openalex.org/keywords/block-matching","display_name":"block matching","score":0.8240000009536743},{"id":"https://openalex.org/keywords/hardware-accelerators","display_name":"hardware accelerators","score":0.6579999923706055},{"id":"https://openalex.org/keywords/systolic-arrays","display_name":"systolic arrays","score":0.9129999876022339},{"id":"https://openalex.org/keywords/parallel-pipelined-architecture","display_name":"parallel pipeline architecture","score":0.8159999847412109},{"id":"https://openalex.org/keywords/video-compression","display_name":"video compression","score":0.39399999380111694},{"id":"https://openalex.org/keywords/fpga-implementation","display_name":"FPGA implementation","score":0.8209999799728394}],"concepts":[{"id":"https://openalex.org/C124828224","wikidata":"https://www.wikidata.org/wiki/Q2632668","display_name":"Macroblock","level":3,"score":0.853075385093689},{"id":"https://openalex.org/C10161872","wikidata":"https://www.wikidata.org/wiki/Q557891","display_name":"Motion estimation","level":2,"score":0.7410359382629395},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7180212736129761},{"id":"https://openalex.org/C43521106","wikidata":"https://www.wikidata.org/wiki/Q2165493","display_name":"Pipeline (software)","level":2,"score":0.5624917149543762},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.5291616916656494},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.5120144486427307},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4804641604423523},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.4675743877887726},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.44172734022140503},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.41391250491142273},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.37335002422332764},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3281010389328003},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.24529913067817688},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.22056043148040771},{"id":"https://openalex.org/C57273362","wikidata":"https://www.wikidata.org/wiki/Q576722","display_name":"Decoding methods","level":2,"score":0.11705648899078369},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.10898402333259583},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1117/12.724042","doi":"https://doi.org/10.1117/12.724042","is_oa":false,"landing_page_url":"https://doi.org/10.1117/12.724042","pdf_url":null,"source":{"id":"https://openalex.org/S183492911","display_name":"Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE","issn_l":"0277-786X","issn":["0277-786X","1996-756X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core","norway-1"],"host_organization":"https://openalex.org/P4310315543","host_organization_name":"SPIE","host_organization_lineage":["https://openalex.org/P4310315543"],"host_organization_lineage_names":["SPIE"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"SPIE Proceedings","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320324492","display_name":"Asociaci\u00f3n Nacional de Universidades e Instituciones de Educaci\u00f3n Superior","ror":"https://ror.org/00tpx5s27"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W1578043166","https://openalex.org/W2141236358","https://openalex.org/W2382452751","https://openalex.org/W2166003990","https://openalex.org/W1536120157","https://openalex.org/W2088565543","https://openalex.org/W2131299130","https://openalex.org/W2068821215","https://openalex.org/W2372530082","https://openalex.org/W2126798395"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"efficient":[3],"integer-pel":[4],"and":[5,32,67,80,94,138,150],"fractional-pel":[6],"motion":[7,52,119],"estimation":[8,120],"VLSI":[9],"architectures":[10,19],"for":[11,25,174],"luma":[12],"video":[13,169],"component":[14],"in":[15,152,155],"H.264/AVC.":[16],"The":[17,50,70,117,142],"proposed":[18],"were":[20],"designed":[21,73],"as":[22],"hardware":[23],"accelerators":[24,36],"32-bit":[26],"processors":[27],"to":[28,42,74,99],"reduce":[29],"computation":[30],"cost":[31],"processing":[33,60],"time.":[34],"Both":[35],"use":[37],"the":[38,44,76,146,164],"full-search":[39],"block-matching":[40],"algorithm":[41],"fulfil":[43],"standard":[45],"requirements":[46],"with":[47,63,109],"maximum":[48,111],"quality.":[49],"integer":[51],"estimator":[53],"is":[54],"composed":[55],"by":[56,128],"a":[57,86,102,110],"systolic":[58],"16x16":[59],"elements":[61],"array":[62,71],"optimal":[64],"memory":[65],"management":[66],"effective":[68,135],"data-path.":[69],"was":[72],"adjust":[75],"search":[77,103],"window":[78,104],"size":[79],"shape":[81,105],"at":[82,160],"macroblock":[83,148],"level":[84],"without":[85],"high":[87],"control":[88],"overhead.":[89],"Simulation":[90],"results":[91,179],"show":[92],"computing":[93],"time":[95,123],"reduction":[96],"from":[97],"21.5%,":[98],"60.7%":[100],"using":[101,184],"different":[106],"than":[107],"square":[108],"PSNR":[112],"degradation":[113],"of":[114,125,130],"0.014":[115],"dB.":[116],"fractional":[118],"architecture":[121,165],"improves":[122],"operation":[124],"previous":[126],"designs":[127],"means":[129],"two":[131],"parallel-pipeline":[132],"stages,":[133],"an":[134],"block":[136],"flow":[137],"faster":[139],"interpolation":[140],"modules.":[141],"design":[143],"can":[144],"process":[145],"41":[147],"partitions":[149],"sub-partitions":[151],"quarter-pel":[153],"resolution":[154],"606":[156],"clock":[157,162],"cycles.":[158],"Operating":[159],"100-MHz":[161],"frequency,":[163],"supports":[166],"720p":[167],"HD":[168],"format":[170],"@":[171],"30":[172],"fps":[173],"one":[175],"reference":[176],"frame.":[177],"Implementation":[178],"based":[180],"on":[181],"FPGA":[182],"devices":[183],"VHDL":[185],"are":[186],"included.":[187]},"counts_by_year":[{"year":2021,"cited_by_count":2}],"updated_date":"2026-11-10T11:39:43.021295","created_date":"2016-06-24T00:00:00"}
