{"id":"https://openalex.org/W1998925396","doi":"https://doi.org/10.1109/asap.2007.4429952","title":"FPGA-Based Efficient Design Approach for Large-Size Two's Complement Squarers","display_name":"FPGA-Based Efficient Design Approach for Large-Size Two's Complement Squarers","publication_year":2007,"publication_date":"2007-07-01","ids":{"openalex":"https://openalex.org/W1998925396","doi":"https://doi.org/10.1109/asap.2007.4429952","mag":"1998925396"},"language":"en","primary_location":{"id":"doi:10.1109/asap.2007.4429952","doi":"https://doi.org/10.1109/asap.2007.4429952","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asap.2007.4429952","pdf_url":null,"source":{"id":"https://openalex.org/S7407086867","display_name":"IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 IEEE International Conf. on Application-specific Systems, Architectures and Processors (ASAP)","raw_type":"proceedings-article"},"volume":null,"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100831306","display_name":"Shuli Gao","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I51768193","display_name":"Royal Military College of Canada","ror":"https://ror.org/04yr71909","country_code":"CA","type":"education","lineage":["https://openalex.org/I51768193"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Shuli Gao","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Royal Military College of Canada, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Royal Military College of Canada, Canada","institution_ids":["https://openalex.org/I51768193"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5034249267","display_name":"Noureddine Chabini","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I51768193","display_name":"Royal Military College of Canada","ror":"https://ror.org/04yr71909","country_code":"CA","type":"education","lineage":["https://openalex.org/I51768193"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Noureddine Chabini","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Royal Military College of Canada, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Royal Military College of Canada, Canada","institution_ids":["https://openalex.org/I51768193"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5002571587","display_name":"D. Al-Khalili","orcid":"https://orcid.org/0000-0002-0079-8417","observed_orcids":["https://orcid.org/0000-0002-0079-8417"]},"institutions":[{"id":"https://openalex.org/I51768193","display_name":"Royal Military College of Canada","ror":"https://ror.org/04yr71909","country_code":"CA","type":"education","lineage":["https://openalex.org/I51768193"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Dhamin Al-Khalili","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Royal Military College of Canada, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Royal Military College of Canada, Canada","institution_ids":["https://openalex.org/I51768193"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5103941091","display_name":"Pierre Langlois","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I45683168","display_name":"Polytechnique Montr\u00e9al","ror":"https://ror.org/05f8d4e86","country_code":"CA","type":"education","lineage":["https://openalex.org/I45683168"]},{"id":"https://openalex.org/I51768193","display_name":"Royal Military College of Canada","ror":"https://ror.org/04yr71909","country_code":"CA","type":"education","lineage":["https://openalex.org/I51768193"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Pierre Langlois","raw_affiliation_strings":["Department of Computer Engineering, \u00c9cole Polytechnique de Montr\u00e9al, Canada","Department of Electrical and Computer Engineering, Royal Military College of Canada, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering, \u00c9cole Polytechnique de Montr\u00e9al, Canada","institution_ids":["https://openalex.org/I45683168"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Royal Military College of Canada, Canada","institution_ids":["https://openalex.org/I51768193"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.9688,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.74654594,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"1","issue":null,"first_page":"18","last_page":"23"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11693","display_name":"Cryptography and Residue Arithmetic","score":0.573199987411499,"subfield":{"id":"https://openalex.org/subfields/1710","display_name":"Information Systems"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11693","display_name":"Cryptography and Residue Arithmetic","score":0.573199987411499,"subfield":{"id":"https://openalex.org/subfields/1710","display_name":"Information Systems"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.22110000252723694,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.09619999676942825,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/fpga-implementation","display_name":"FPGA implementation","score":0.6209999918937683},{"id":"https://openalex.org/keywords/embedded-multipliers","display_name":"embedded multipliers","score":0.8289999961853027},{"id":"https://openalex.org/keywords/partial-product-addition","display_name":"partial product addition","score":0.8569999933242798},{"id":"https://openalex.org/keywords/signed-multiplication","display_name":"signed multiplication","score":0.6380000114440918},{"id":"https://openalex.org/keywords/delay-reduction","display_name":"delay reduction","score":0.5690000057220459},{"id":"https://openalex.org/keywords/xilinx-spartan-3","display_name":"Xilinx Spartan-3","score":0.7239999771118164}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8021284341812134},{"id":"https://openalex.org/C55526617","wikidata":"https://www.wikidata.org/wiki/Q719375","display_name":"Operand","level":2,"score":0.7591880559921265},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.7591387033462524},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7483373880386353},{"id":"https://openalex.org/C112313634","wikidata":"https://www.wikidata.org/wiki/Q7886648","display_name":"Complement (music)","level":5,"score":0.5701004266738892},{"id":"https://openalex.org/C2781089630","wikidata":"https://www.wikidata.org/wiki/Q21856745","display_name":"Realization (probability)","level":2,"score":0.5291624069213867},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.4665273129940033},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.45398253202438354},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.3803931772708893},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.35769417881965637},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.32306718826293945},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.16812118887901306},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.07072553038597107},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0},{"id":"https://openalex.org/C104317684","wikidata":"https://www.wikidata.org/wiki/Q7187","display_name":"Gene","level":2,"score":0.0},{"id":"https://openalex.org/C188082640","wikidata":"https://www.wikidata.org/wiki/Q1780899","display_name":"Complementation","level":4,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C55493867","wikidata":"https://www.wikidata.org/wiki/Q7094","display_name":"Biochemistry","level":1,"score":0.0},{"id":"https://openalex.org/C127716648","wikidata":"https://www.wikidata.org/wiki/Q104053","display_name":"Phenotype","level":3,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/asap.2007.4429952","doi":"https://doi.org/10.1109/asap.2007.4429952","is_oa":false,"landing_page_url":"https://doi.org/10.1109/asap.2007.4429952","pdf_url":null,"source":{"id":"https://openalex.org/S7407086867","display_name":"IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 IEEE International Conf. on Application-specific Systems, Architectures and Processors (ASAP)","raw_type":"proceedings-article"},{"id":"pmh:oai:publications.polymtl.ca:21955","doi":null,"is_oa":false,"landing_page_url":"https://publications.polymtl.ca/21955/","pdf_url":null,"source":{"id":"https://openalex.org/S4306401013","display_name":"PolyPublie (\u00c9cole Polytechnique de Montr\u00e9al)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/I45683168","host_organization_name":"Polytechnique Montr\u00e9al","host_organization_lineage":["https://openalex.org/I45683168"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Gao, S., Chabini, N., Al-Khalili, D., & Langlois, J. M. P. (2007, July). FPGA-based efficient design approach for large-size two's complement squarers [Paper]. IEEE International Conference on Application-specific Systems, Architectures and Processors, Montr\u00e9al, Qu\u00e9bec.","raw_type":"http://purl.org/coar/resource_type/c_5794"}],"best_oa_location":null,"sustainable_development_goals":[],"sustainable_development_goals_aurora":[{"score":0.5199999809265137,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"study_designs":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":21,"referenced_works":["https://openalex.org/W1549332819","https://openalex.org/W1552895118","https://openalex.org/W1584008964","https://openalex.org/W1588197472","https://openalex.org/W1624515072","https://openalex.org/W2048712324","https://openalex.org/W2048773562","https://openalex.org/W2096864090","https://openalex.org/W2097988027","https://openalex.org/W2103530663","https://openalex.org/W2104839467","https://openalex.org/W2115495417","https://openalex.org/W2124088784","https://openalex.org/W2124879637","https://openalex.org/W2129614729","https://openalex.org/W2132535970","https://openalex.org/W2138122458","https://openalex.org/W2138278630","https://openalex.org/W2139946453","https://openalex.org/W2625218749","https://openalex.org/W4210830821"],"related_works":["https://openalex.org/W2131025090","https://openalex.org/W2118847419","https://openalex.org/W2088602259","https://openalex.org/W2124879637","https://openalex.org/W2134694462","https://openalex.org/W4403023860","https://openalex.org/W2144014713","https://openalex.org/W4321637147","https://openalex.org/W2097232115","https://openalex.org/W1572448354"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"an":[3,114],"optimized":[4,40],"design":[5,86],"approach":[6,55,104],"of":[7,39,45,48,62,118,122,125],"two's":[8],"complement":[9],"large-size":[10],"squarers":[11,63],"using":[12],"embedded":[13,126],"multipliers":[14,127],"in":[15],"FPGAs.":[16],"The":[17,74,99,120],"realization":[18,44],"is":[19,52,128],"based":[20],"on":[21,80],"Baugh-Wooley's":[22],"algorithm,":[23],"which":[24],"partitions":[25],"the":[26,43,49,60,91,123,134],"multiplication":[27],"into":[28],"unsigned":[29],"and":[30,78,88,94],"signed":[31],"sections.":[32],"To":[33],"achieve":[34],"efficient":[35],"implementation,":[36,93],"a":[37],"set":[38],"schemes":[41],"for":[42,64],"multi-level":[46],"additions":[47],"partial":[50],"products":[51],"proposed.":[53],"Our":[54],"has":[56],"been":[57],"evaluated":[58],"through":[59],"implementation":[61],"operands":[65],"with":[66,83,90,95,113,133],"sizes":[67],"ranging":[68],"from":[69],"20":[70],"to":[71,111],"128":[72],"bits.":[73],"designs":[75],"are":[76],"synthesized":[77],"implemented":[79],"Xilinx'":[81,96],"Spartan-3":[82],"ISE":[84],"8.1":[85],"platform":[87],"compared":[89,132],"standard":[92,135],"IP":[97],"Core.":[98],"results":[100],"indicate":[101],"that":[102],"our":[103],"offers":[105],"substantial":[106],"LUT":[107],"savings":[108],"by":[109,130],"up":[110],"52%":[112],"average":[115],"delay":[116],"reduction":[117],"13%.":[119],"usage":[121],"number":[124],"reduced":[129],"38%":[131],"schemes.":[136]},"counts_by_year":[{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":2},{"year":2012,"cited_by_count":1}],"updated_date":"2026-10-27T15:51:10.671819","created_date":"2016-06-24T00:00:00"}