{"id":"https://openalex.org/W1998425871","doi":"https://doi.org/10.1109/40.31485","title":"Introducing the Intel i860 64-bit microprocessor","display_name":"Introducing the Intel i860 64-bit microprocessor","publication_year":1989,"publication_date":"1989-08-01","ids":{"openalex":"https://openalex.org/W1998425871","doi":"https://doi.org/10.1109/40.31485","mag":"1998425871"},"language":"en","primary_location":{"id":"doi:10.1109/40.31485","doi":"https://doi.org/10.1109/40.31485","is_oa":false,"landing_page_url":"https://doi.org/10.1109/40.31485","pdf_url":null,"source":{"id":"https://openalex.org/S59697426","display_name":"IEEE Micro","issn_l":"0272-1732","issn":["0272-1732","1937-4143"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core","dongbi-a","jufo-3","norway-2","poland-140","russia-white-list-1"],"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Micro","raw_type":"journal-article"},"volume":null,"type":"article","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5035079436","display_name":"Leslie Kohn","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"L. Kohn","raw_affiliation_strings":["Intel Corp., Santa Clara, CA","Intel Corp., Santa Clara, CA, , USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corp., Santa Clara, CA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corp., Santa Clara, CA, , USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5036021187","display_name":"Neal Margulis","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"N. Margulis","raw_affiliation_strings":["Architecture and system design, Intel Corp","Intel Corp., Santa Clara, CA, , USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Architecture and system design, Intel Corp","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corp., Santa Clara, CA, , USA","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":{"value":2995,"currency":"USD","value_usd":2995},"apc_paid":null,"fwci":7.1646,"has_fulltext":false,"cited_by_count":54,"citation_normalized_percentile":{"value":0.96983105,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":87,"max":97},"biblio":{"volume":"9","issue":"4","first_page":"15","last_page":"30"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9922000169754028,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9922000169754028,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.002400000113993883,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.002099999925121665,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/intel-i860","display_name":"Intel i860","score":0.9750000238418579},{"id":"https://openalex.org/keywords/64-bit-microprocessor","display_name":"64-bit microprocessor","score":0.9729999899864197},{"id":"https://openalex.org/keywords/risc-architecture","display_name":"RISC architecture","score":0.859000027179718},{"id":"https://openalex.org/keywords/parallel-instruction-execution","display_name":"parallel instruction execution","score":0.7120000123977661},{"id":"https://openalex.org/keywords/floating-point-unit","display_name":"floating-point unit","score":0.7419999837875366},{"id":"https://openalex.org/keywords/graphics-hardware","display_name":"graphics hardware","score":0.5170000195503235},{"id":"https://openalex.org/keywords/memory-management","display_name":"memory management","score":0.9769999980926514},{"id":"https://openalex.org/keywords/bus-interface","display_name":"bus interface","score":0.8450000286102295},{"id":"https://openalex.org/keywords/supercomputer-architecture","display_name":"supercomputer architecture","score":0.5019999742507935},{"id":"https://openalex.org/keywords/processor-design","display_name":"processor design","score":0.48100000619888306}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8075580596923828},{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.630700945854187},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.5798818469047546},{"id":"https://openalex.org/C2776303644","wikidata":"https://www.wikidata.org/wiki/Q1020499","display_name":"Interfacing","level":2,"score":0.5730345249176025},{"id":"https://openalex.org/C126298526","wikidata":"https://www.wikidata.org/wiki/Q189376","display_name":"Reduced instruction set computing","level":3,"score":0.566108226776123},{"id":"https://openalex.org/C56005371","wikidata":"https://www.wikidata.org/wiki/Q209860","display_name":"PowerPC","level":3,"score":0.5602303147315979},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.5489618182182312},{"id":"https://openalex.org/C86111242","wikidata":"https://www.wikidata.org/wiki/Q859595","display_name":"Coprocessor","level":2,"score":0.5449106693267822},{"id":"https://openalex.org/C21442007","wikidata":"https://www.wikidata.org/wiki/Q1027879","display_name":"Graphics","level":2,"score":0.5323047637939453},{"id":"https://openalex.org/C75695347","wikidata":"https://www.wikidata.org/wiki/Q225147","display_name":"32-bit","level":2,"score":0.4866257607936859},{"id":"https://openalex.org/C156972235","wikidata":"https://www.wikidata.org/wiki/Q1443434","display_name":"Instructions per cycle","level":3,"score":0.46031567454338074},{"id":"https://openalex.org/C76399640","wikidata":"https://www.wikidata.org/wiki/Q189401","display_name":"Virtual memory","level":4,"score":0.4517117142677307},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.4496394693851471},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4429372251033783},{"id":"https://openalex.org/C33652231","wikidata":"https://www.wikidata.org/wiki/Q194368","display_name":"16-bit","level":2,"score":0.41685113310813904},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.40637001395225525},{"id":"https://openalex.org/C49154492","wikidata":"https://www.wikidata.org/wiki/Q5300","display_name":"Central processing unit","level":2,"score":0.37577784061431885},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.27191466093063354},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.10871455073356628}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/40.31485","doi":"https://doi.org/10.1109/40.31485","is_oa":false,"landing_page_url":"https://doi.org/10.1109/40.31485","pdf_url":null,"source":{"id":"https://openalex.org/S59697426","display_name":"IEEE Micro","issn_l":"0272-1732","issn":["0272-1732","1937-4143"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core","dongbi-a","jufo-3","norway-2","poland-140","russia-white-list-1"],"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Micro","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2080310026","https://openalex.org/W1985970291","https://openalex.org/W4255543570","https://openalex.org/W2104680790","https://openalex.org/W4236499371","https://openalex.org/W4231234604","https://openalex.org/W1918018625","https://openalex.org/W2138634662","https://openalex.org/W1816859267","https://openalex.org/W2187790578"],"abstract_inverted_index":{"The":[0],"authors":[1],"describe":[2],"the":[3,24,37],"single-chip":[4],"i860":[5],"CPU,":[6],"a":[7,52],"64-bit,":[8],"RISC":[9,38],"(reduced-instruction-set-computer)-based":[10],"microprocessor":[11],"that":[12],"executes":[13],"parallel":[14],"instructions":[15],"using":[16],"mainframe":[17],"and":[18,32,49],"supercomputer":[19],"architectural":[20],"concepts.":[21],"They":[22,35],"designed":[23],"1,000,000-transistor,":[25],"10-mm*15-mm":[26],"processor":[27],"for":[28],"balanced":[29],"integer,":[30],"floating-point,":[31],"graphics":[33],"performance.":[34],"discuss":[36],"core,":[39],"memory":[40],"management,":[41],"floating-point":[42],"unit,":[43],"graphics,":[44],"bus":[45],"interface,":[46],"software":[47],"support,":[48],"interfacing":[50],"to":[51],"DRAM":[53],"system.>":[54]},"counts_by_year":[{"year":2022,"cited_by_count":3},{"year":2021,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":2},{"year":2013,"cited_by_count":3}],"updated_date":"2026-11-07T11:25:07.637180","created_date":"2016-06-24T00:00:00"}
