{"id":"https://openalex.org/W1997399059","doi":"https://doi.org/10.1109/drc.2012.6256997","title":"Epitaxialy defined (ED) FinFET: to reduce VT variability and enable multiple VT","display_name":"Epitaxialy defined (ED) FinFET: to reduce VT variability and enable multiple VT","publication_year":2012,"publication_date":"2012-06-01","ids":{"openalex":"https://openalex.org/W1997399059","doi":"https://doi.org/10.1109/drc.2012.6256997","mag":"1997399059"},"language":"en","primary_location":{"id":"doi:10.1109/drc.2012.6256997","doi":"https://doi.org/10.1109/drc.2012.6256997","is_oa":false,"landing_page_url":"https://doi.org/10.1109/drc.2012.6256997","pdf_url":null,"source":{"id":"https://openalex.org/S4210174617","display_name":"Conference digest","issn_l":"1548-3770","issn":["1548-3770","2640-6853"],"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"70th Device Research Conference","raw_type":"proceedings-article"},"volume":null,"type":"conference-paper","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5041229044","display_name":"S. Mittal","orcid":"https://orcid.org/0000-0001-5418-5053","observed_orcids":["https://orcid.org/0000-0001-5418-5053"]},"institutions":[{"id":"https://openalex.org/I162827531","display_name":"Indian Institute of Technology Bombay","ror":"https://ror.org/02qyf5152","country_code":"IN","type":"education","lineage":["https://openalex.org/I162827531"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"S. Mittal","raw_affiliation_strings":["Indian Institute of Technology Bombay, Mumbai, Maharashtra, IN"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Indian Institute of Technology Bombay, Mumbai, Maharashtra, IN","institution_ids":["https://openalex.org/I162827531"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101995842","display_name":"Shashank Gupta","orcid":"https://orcid.org/0000-0002-9000-1095","observed_orcids":["https://orcid.org/0000-0002-9000-1095"]},"institutions":[{"id":"https://openalex.org/I193427800","display_name":"Applied Materials (United States)","ror":"https://ror.org/04h1q4c89","country_code":"US","type":"company","lineage":["https://openalex.org/I193427800"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"S. Gupta","raw_affiliation_strings":["Applied Materials Inc., Santa Clara, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Applied Materials Inc., Santa Clara, USA","institution_ids":["https://openalex.org/I193427800"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5063395423","display_name":"Aneesh Nainani","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I193427800","display_name":"Applied Materials (United States)","ror":"https://ror.org/04h1q4c89","country_code":"US","type":"company","lineage":["https://openalex.org/I193427800"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"A. Nainani","raw_affiliation_strings":["Applied Materials Inc., Santa Clara, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Applied Materials Inc., Santa Clara, USA","institution_ids":["https://openalex.org/I193427800"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5047081628","display_name":"Mathew C. Abraham","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I193427800","display_name":"Applied Materials (United States)","ror":"https://ror.org/04h1q4c89","country_code":"US","type":"company","lineage":["https://openalex.org/I193427800"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"M.C. Abraham","raw_affiliation_strings":["Applied Materials Inc., Santa Clara, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Applied Materials Inc., Santa Clara, USA","institution_ids":["https://openalex.org/I193427800"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111805728","display_name":"Klaus K. Schuegraf","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I193427800","display_name":"Applied Materials (United States)","ror":"https://ror.org/04h1q4c89","country_code":"US","type":"company","lineage":["https://openalex.org/I193427800"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"K. Schuegraf","raw_affiliation_strings":["Applied Materials Inc., Santa Clara, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Applied Materials Inc., Santa Clara, USA","institution_ids":["https://openalex.org/I193427800"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5076966798","display_name":"Saurabh Lodha","orcid":"https://orcid.org/0000-0002-0690-3169","observed_orcids":["https://orcid.org/0000-0002-0690-3169"]},"institutions":[{"id":"https://openalex.org/I162827531","display_name":"Indian Institute of Technology Bombay","ror":"https://ror.org/02qyf5152","country_code":"IN","type":"education","lineage":["https://openalex.org/I162827531"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"S. Lodha","raw_affiliation_strings":["CEN Department of EE, Indian Institute of Technology, Bombay, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"CEN Department of EE, Indian Institute of Technology, Bombay, India","institution_ids":["https://openalex.org/I162827531"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5073593093","display_name":"Udayan Ganguly","orcid":"https://orcid.org/0000-0002-1498-5993","observed_orcids":["https://orcid.org/0000-0002-1498-5993"]},"institutions":[{"id":"https://openalex.org/I162827531","display_name":"Indian Institute of Technology Bombay","ror":"https://ror.org/02qyf5152","country_code":"IN","type":"education","lineage":["https://openalex.org/I162827531"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"U. Ganguly","raw_affiliation_strings":["CEN Department of EE, Indian Institute of Technology, Bombay, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"CEN Department of EE, Indian Institute of Technology, Bombay, India","institution_ids":["https://openalex.org/I162827531"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.65,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.81070337,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"7","issue":null,"first_page":"127","last_page":"128"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9628999829292297,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9628999829292297,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.02250000089406967,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.007799999788403511,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/threshold-voltage-variation","display_name":"threshold voltage variation","score":0.8270000219345093},{"id":"https://openalex.org/keywords/multiple-threshold-voltages","display_name":"multiple threshold voltages","score":0.8339999914169312},{"id":"https://openalex.org/keywords/line-edge-roughness","display_name":"line edge roughness","score":0.9660000205039978},{"id":"https://openalex.org/keywords/random-dopant-fluctuation","display_name":"random dopant fluctuation","score":0.9829999804496765},{"id":"https://openalex.org/keywords/short-channel-effects","display_name":"short-channel effects","score":0.675000011920929},{"id":"https://openalex.org/keywords/power-performance-trade-off","display_name":"power-performance tradeoff","score":0.5929999947547913}],"concepts":[{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5654534101486206},{"id":"https://openalex.org/C162307627","wikidata":"https://www.wikidata.org/wiki/Q204833","display_name":"Enhanced Data Rates for GSM Evolution","level":2,"score":0.49720504879951477},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.4419345259666443},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.4418230652809143},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.4209817051887512},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.3953646421432495},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.35695981979370117},{"id":"https://openalex.org/C49040817","wikidata":"https://www.wikidata.org/wiki/Q193091","display_name":"Optoelectronics","level":1,"score":0.35526883602142334},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.32439863681793213},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2068173885345459},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.205616295337677},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.20208004117012024}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/drc.2012.6256997","doi":"https://doi.org/10.1109/drc.2012.6256997","is_oa":false,"landing_page_url":"https://doi.org/10.1109/drc.2012.6256997","pdf_url":null,"source":{"id":"https://openalex.org/S4210174617","display_name":"Conference digest","issn_l":"1548-3770","issn":["1548-3770","2640-6853"],"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"70th Device Research Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1977413415","https://openalex.org/W2114131053","https://openalex.org/W2137891515","https://openalex.org/W2139063350","https://openalex.org/W2157104754","https://openalex.org/W2157321309","https://openalex.org/W3150050634"],"related_works":["https://openalex.org/W2322129326","https://openalex.org/W2546710229","https://openalex.org/W2085163164","https://openalex.org/W1969550480","https://openalex.org/W2338629077","https://openalex.org/W2580935718","https://openalex.org/W4386862076","https://openalex.org/W2588169957","https://openalex.org/W2075525009","https://openalex.org/W2001986306"],"abstract_inverted_index":{"Device":[0],"variability":[1,14,82,159],"has":[2,37],"become":[3],"a":[4],"major":[5],"concern":[6],"for":[7,121,134],"CMOS":[8],"technology":[9,92,112,123,131],"[1].":[10],"Various":[11],"sources":[12],"of":[13,32,43,72,96,99],"include":[15],"Random":[16],"Dopant":[17],"Fluctuation":[18],"(RDF),":[19],"Gate":[20],"Edge":[21,26],"Roughness":[22,27],"(GER)":[23],"and":[24,74,93,167],"Line":[25],"(LER)":[28],"[2].":[29,83],"The":[30],"introduction":[31],"FinFETs":[33],"at":[34],"22nm":[35],"node":[36],"two":[38],"issues.":[39],"Firstly,":[40],"the":[41,54,69,85,97,125],"effect":[42,67],"RDF":[44],"is":[45,108,119,127,132],"considerably":[46],"reduced":[47],"due":[48],"to":[49,63,79,150,165],"undoped":[50],"fins":[51],"[3].":[52],"But":[53],"aggressive":[55],"fin":[56,126],"width":[57],"(Wfin)":[58],"requirement":[59],"(~":[60],"Lg/3":[61],"[4])":[62],"reduce":[64,157],"short":[65],"channel":[66],"aggravates":[68],"electrical":[70],"impact":[71],"LER":[73,166],"makes":[75],"it":[76],"greatest":[77],"contributor":[78],"patterning":[80],"induced":[81],"Moreover,":[84],"edge":[86],"roughness":[87],"does":[88],"not":[89],"scale":[90],"with":[91],"remains":[94],"independent":[95],"type":[98],"lithography":[100],"used":[101],"[5].":[102],"Secondly,":[103],"multiple":[104,170],"threshold":[105],"voltage":[106],"(VT)":[107],"achieved":[109],"in":[110,163],"planar":[111],"by":[113,139,160],"various":[114],"patterned":[115,179],"implant":[116,180],"steps,":[117],"which":[118,154],"unavailable":[120],"FinFET":[122,152],"as":[124],"undoped.":[128],"Multiple":[129],"VTtransistor":[130],"essential":[133],"power":[135],"vs.":[136],"performance":[137],"optimization":[138],"circuit":[140],"designers":[141],"[6].":[142],"In":[143],"this":[144],"work,":[145],"we":[146],"propose":[147],"an":[148],"alternative":[149],"conventional":[151],"structure":[153],"can":[155],"(a)":[156],"overall":[158],"4\u00d7":[161],"reduction":[162],"sensitivity":[164],"(b)":[168],"enable":[169],"VTby":[171],"applying":[172],"body":[173],"bias":[174],"dynamically":[175],"without":[176],"any":[177],"costly":[178],"steps.":[181]},"counts_by_year":[{"year":2016,"cited_by_count":1},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":2}],"updated_date":"2026-10-14T16:39:01.820549","created_date":"2016-06-24T00:00:00"}
