{"id":"https://openalex.org/W1996807822","doi":"https://doi.org/10.1049/ip-g-1.1984.0011","title":"Part 1: VLSI implementation of an optimised hierarchical multiplier","display_name":"Part 1: VLSI implementation of an optimised hierarchical multiplier","publication_year":1984,"publication_date":"1984-01-01","ids":{"openalex":"https://openalex.org/W1996807822","doi":"https://doi.org/10.1049/ip-g-1.1984.0011","mag":"1996807822"},"language":"en","primary_location":{"id":"doi:10.1049/ip-g-1.1984.0011","doi":"https://doi.org/10.1049/ip-g-1.1984.0011","is_oa":false,"landing_page_url":"https://doi.org/10.1049/ip-g-1.1984.0011","pdf_url":null,"source":{"id":"https://openalex.org/S4210219774","display_name":"IEE Proceedings G (Electronic Circuits and Systems)","issn_l":"0143-7089","issn":["0143-7089","2053-7964"],"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEE Proceedings G (Electronic Circuits and Systems)","raw_type":"journal-article"},"volume":null,"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5019590900","display_name":"H.C. Yung","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I84884186","display_name":"Newcastle University","ror":"https://ror.org/01kj2bm70","country_code":"GB","type":"education","lineage":["https://openalex.org/I84884186"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"H.C. Yung","raw_affiliation_strings":["Department of Electrical & Electronic Engineering, Merz Laboratories, University of Newcastle upon Tyne, Newcastle upon Tyne, UK"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical & Electronic Engineering, Merz Laboratories, University of Newcastle upon Tyne, Newcastle upon Tyne, UK","institution_ids":["https://openalex.org/I84884186"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5072710281","display_name":"CR Allen","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I84884186","display_name":"Newcastle University","ror":"https://ror.org/01kj2bm70","country_code":"GB","type":"education","lineage":["https://openalex.org/I84884186"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"C.R. Allen","raw_affiliation_strings":["Department of Electrical & Electronic Engineering, Merz Laboratories, University of Newcastle upon Tyne, Newcastle upon Tyne, UK"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical & Electronic Engineering, Merz Laboratories, University of Newcastle upon Tyne, Newcastle upon Tyne, UK","institution_ids":["https://openalex.org/I84884186"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I84884186"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.1921062,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":93},"biblio":{"volume":"131","issue":"2","first_page":"56","last_page":"56"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.7865999937057495,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.7865999937057495,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.2046000063419342,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.0019000000320374966,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/vlsi-implementation","display_name":"VLSI implementation","score":0.8949999809265137},{"id":"https://openalex.org/keywords/full-adder","display_name":"full adder","score":0.8999999761581421},{"id":"https://openalex.org/keywords/area-time-complexity","display_name":"area-time complexity","score":0.7080000042915344},{"id":"https://openalex.org/keywords/high-speed-multiplication","display_name":"high-speed multiplication","score":0.6579999923706055}],"concepts":[{"id":"https://openalex.org/C124584101","wikidata":"https://www.wikidata.org/wiki/Q1053266","display_name":"Multiplier (economics)","level":2,"score":0.8991000056266785},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.7202689051628113},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.6773216724395752},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.6137462854385376},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4891543686389923},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.42168253660202026},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.39319342374801636},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.1071370542049408},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.05597594380378723},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1049/ip-g-1.1984.0011","doi":"https://doi.org/10.1049/ip-g-1.1984.0011","is_oa":false,"landing_page_url":"https://doi.org/10.1049/ip-g-1.1984.0011","pdf_url":null,"source":{"id":"https://openalex.org/S4210219774","display_name":"IEE Proceedings G (Electronic Circuits and Systems)","issn_l":"0143-7089","issn":["0143-7089","2053-7964"],"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEE Proceedings G (Electronic Circuits and Systems)","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1511375762","https://openalex.org/W1548340326","https://openalex.org/W1666015432","https://openalex.org/W1888241759","https://openalex.org/W2034363187","https://openalex.org/W2135030554","https://openalex.org/W2165495918"],"related_works":["https://openalex.org/W2051053729","https://openalex.org/W2153449359","https://openalex.org/W2278970636","https://openalex.org/W2596775527","https://openalex.org/W2043243784","https://openalex.org/W1966133222","https://openalex.org/W2186708314","https://openalex.org/W2364208051","https://openalex.org/W1888241759","https://openalex.org/W2977494642"],"abstract_inverted_index":{"The":[0,16,64],"implementation":[1,91],"and":[2,8,28,33,40,78],"optimisation":[3],"procedure":[4],"of":[5,35,43],"a":[6,22,29],"regular,":[7],"recursive,":[9],"high-speed":[10],"N-bit":[11],"multiplier":[12,26,48,65,90],"design":[13,17,45],"is":[14,66,86,92],"presented.":[15],"comprises":[18],"two":[19],"simple":[20],"cells:":[21],"2":[23],"\u00d7":[24],"2-bit":[25],"PLA":[27],"full":[30],"adder":[31],"PLA,":[32],"most":[34],"the":[36,44,61,72],"interconnections":[37],"are":[38],"local":[39],"regular.":[41],"Extension":[42],"to":[46,82],"any":[47],"word":[49],"size":[50],"can":[51],"be":[52],"done":[53],"by":[54],"simply":[55],"combining":[56],"smaller":[57],"cell":[58],"blocks":[59],"following":[60],"same":[62],"algorithm.":[63],"optimised":[67],"for":[68],"area-time":[69],"complexity,":[70],"using":[71],"analysis":[73],"presented":[74],"in":[75,94],"Part":[76],"2,":[77],"its":[79],"performance":[80],"relative":[81],"previously":[83],"reported":[84],"designs":[85],"good.":[87],"A":[88],"four-bit":[89],"discussed":[93],"detail.":[95]},"counts_by_year":[{"year":2020,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2016-06-24T00:00:00"}