{"id":"https://openalex.org/W1996796834","doi":"https://doi.org/10.1109/vlsi.design.2010.59","title":"A 90mW/GFlop 3.4GHz Reconfigurable Fused/Continuous Multiply-Accumulator for Floating-Point and Integer Operands in 65nm","display_name":"A 90mW/GFlop 3.4GHz Reconfigurable Fused/Continuous Multiply-Accumulator for Floating-Point and Integer Operands in 65nm","publication_year":2010,"publication_date":"2010-01-01","ids":{"openalex":"https://openalex.org/W1996796834","doi":"https://doi.org/10.1109/vlsi.design.2010.59","mag":"1996796834"},"language":"en","primary_location":{"id":"doi:10.1109/vlsi.design.2010.59","doi":"https://doi.org/10.1109/vlsi.design.2010.59","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi.design.2010.59","pdf_url":null,"source":{"id":"https://openalex.org/S4306419912","display_name":"International Conference on VLSI Design","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 23rd International Conference on VLSI Design","raw_type":"proceedings-article"},"volume":null,"type":"conference-paper","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":null,"display_name":"Shailendra Jain","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Shailendra Jain","raw_affiliation_strings":["Intel Corporation, USA","Intel Corporation, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, CA, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5081522570","display_name":"Vasantha Erraguntla","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Vasantha Erraguntla","raw_affiliation_strings":["Intel Corporation, USA","Intel Corporation, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, CA, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102778960","display_name":"Sriram R. Vangal","orcid":"https://orcid.org/0000-0003-1548-9876","observed_orcids":["https://orcid.org/0000-0003-1548-9876"]},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sriram R. Vangal","raw_affiliation_strings":["Intel Corporation, USA","Intel Corporation, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, CA, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5081186735","display_name":"Yatin Hoskote","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yatin Hoskote","raw_affiliation_strings":["Intel Corporation, USA","Intel Corporation, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, CA, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5112900267","display_name":"Nitin Borkar","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Nitin Borkar","raw_affiliation_strings":["Intel Corporation, USA","Intel Corporation, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, CA, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5077146547","display_name":"Tulasi Mandepudi","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Tulasi Mandepudi","raw_affiliation_strings":["Intel Corporation, USA","Intel Corporation, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, CA, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5113553900","display_name":"V.P. Karthik","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I46308248","display_name":"Engineers India (India)","ror":"https://ror.org/05wy2at76","country_code":"IN","type":"company","lineage":["https://openalex.org/I46308248"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"V.P. Karthik","raw_affiliation_strings":["Analog Devices India Private Limited, India","Analog Devices India Pvt. Ltd., India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Analog Devices India Private Limited, India","institution_ids":["https://openalex.org/I46308248"]},{"raw_affiliation_string":"Analog Devices India Pvt. Ltd., India","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":4.7057,"has_fulltext":false,"cited_by_count":17,"citation_normalized_percentile":{"value":0.95839246,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":88,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"252","last_page":"257"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9394999742507935,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9394999742507935,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.05689999833703041,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.0006000000284984708,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/multiply-accumulate-unit","display_name":"multiply-accumulate unit","score":0.9179999828338623},{"id":"https://openalex.org/keywords/floating-point-arithmetic","display_name":"floating-point arithmetic","score":0.8880000114440918},{"id":"https://openalex.org/keywords/integer-arithmetic","display_name":"integer arithmetic","score":0.8169999718666077},{"id":"https://openalex.org/keywords/power-gating","display_name":"power gating","score":0.906000018119812},{"id":"https://openalex.org/keywords/leakage-power-reduction","display_name":"leakage power reduction","score":0.9620000123977661},{"id":"https://openalex.org/keywords/energy-efficiency","display_name":"energy efficiency","score":0.6930000185966492},{"id":"https://openalex.org/keywords/pipelined-multiplier","display_name":"pipelined multiplier","score":0.828000009059906},{"id":"https://openalex.org/keywords/65-nm-cmos","display_name":"65 nm CMOS","score":0.7630000114440918}],"concepts":[{"id":"https://openalex.org/C55526617","wikidata":"https://www.wikidata.org/wiki/Q719375","display_name":"Operand","level":2,"score":0.7128646969795227},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6156677007675171},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.6051344871520996},{"id":"https://openalex.org/C2078106","wikidata":"https://www.wikidata.org/wiki/Q14906620","display_name":"Accumulator (cryptography)","level":2,"score":0.6038670539855957},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.597000002861023},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.5295054912567139},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4615933895111084},{"id":"https://openalex.org/C3826847","wikidata":"https://www.wikidata.org/wiki/Q188768","display_name":"FLOPS","level":2,"score":0.4545140266418457},{"id":"https://openalex.org/C84211073","wikidata":"https://www.wikidata.org/wiki/Q117879","display_name":"Floating point","level":2,"score":0.45096734166145325},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4266449213027954},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4161613881587982},{"id":"https://openalex.org/C124584101","wikidata":"https://www.wikidata.org/wiki/Q1053266","display_name":"Multiplier (economics)","level":2,"score":0.4148578643798828},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3806474208831787},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.2983238697052002},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2612394392490387},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.17735692858695984},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vlsi.design.2010.59","doi":"https://doi.org/10.1109/vlsi.design.2010.59","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi.design.2010.59","pdf_url":null,"source":{"id":"https://openalex.org/S4306419912","display_name":"International Conference on VLSI Design","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 23rd International Conference on VLSI Design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":3,"referenced_works":["https://openalex.org/W1602562456","https://openalex.org/W2145071646","https://openalex.org/W2155385791"],"related_works":["https://openalex.org/W2155385791","https://openalex.org/W2167435427","https://openalex.org/W2167307228","https://openalex.org/W2009732869","https://openalex.org/W7160900226","https://openalex.org/W7124957409","https://openalex.org/W2122960224","https://openalex.org/W2391539665","https://openalex.org/W2112878744","https://openalex.org/W2967182382"],"abstract_inverted_index":{"This":[0,19],"paper":[1],"describes":[2],"energy":[3,49,128],"efficient":[4],"and":[5,14,22,38,56,83,96,135],"reconfigurable":[6],"fused/continuous":[7],"Multiply-Accumulator":[8],"(MAC)":[9],"architecture":[10],"for":[11,99],"single-precision":[12],"Floating-point":[13],"16-bit":[15],"signed":[16],"integer":[17],"operands.":[18],"eight-stage":[20],"pipelined":[21,31],"single-cycle":[23],"throughput":[24],"MAC":[25],"design":[26,69,105,120],"contains":[27],"a":[28,103],"bit":[29],"level":[30],"multiplier,":[32,94],"followed":[33],"by":[34],"fast":[35],"sparse-tree":[36],"adder":[37],"single":[39],"cycle":[40],"accumulator":[41,95],"loop":[42],"with":[43,126],"delayed":[44],"normalization":[45,97],"logic.":[46],"Operation":[47],"driven":[48],"control":[50],"is":[51,64],"achieved":[52],"using":[53],"dynamic":[54],"clock":[55],"fine":[57],"grained":[58],"power":[59,75],"gating":[60,63],"techniques.":[61],"Power":[62],"employed":[65],"in":[66,76,92,112],"98%":[67],"of":[68,73,88,106,124,130],"to":[70],"save":[71],"79%":[72],"leakage":[74],"idle":[77],"mode,":[78],"at":[79,133],"1.2":[80],"V":[81],"supply":[82],"110":[84],"C.":[85],"The":[86,118],"use":[87],"fully":[89],"shared":[90],"logic":[91],"the":[93],"blocks":[98],"different":[100],"operations":[101],"enables":[102],"compact":[104],"0.54":[107],"mm2containing":[108],"117":[109],"K":[110],"transistors":[111],"eight-metal":[113],"65":[114],"nm":[115],"CMOS":[116],"technology.":[117],"15-FO4":[119],"provides":[121],"6.8":[122],"GFLOPS":[123],"performance":[125],"total":[127],"efficiency":[129],"90":[131],"mW/GFLOP":[132],"1.2V":[134],"3.4":[136],"GHz":[137],"operation.":[138]},"counts_by_year":[{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":2},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":5},{"year":2012,"cited_by_count":3}],"updated_date":"2026-11-07T11:25:07.637180","created_date":"2016-06-24T00:00:00"}
