{"id":"https://openalex.org/W1993715670","doi":"https://doi.org/10.1109/c-m.1981.220596","title":"Functionally Parallel Architecture for Array Processors","display_name":"Functionally Parallel Architecture for Array Processors","publication_year":1981,"publication_date":"1981-09-01","ids":{"openalex":"https://openalex.org/W1993715670","doi":"https://doi.org/10.1109/c-m.1981.220596","mag":"1993715670"},"language":"en","primary_location":{"id":"doi:10.1109/c-m.1981.220596","doi":"https://doi.org/10.1109/c-m.1981.220596","is_oa":false,"landing_page_url":"https://doi.org/10.1109/c-m.1981.220596","pdf_url":null,"source":{"id":"https://openalex.org/S178916657","display_name":"Computer","issn_l":"0018-9162","issn":["0018-9162","1558-0814"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["anvur-class-a","anvur-scientific","cwts-core","dongbi-b","jufo-2","norway-2","poland-70","russia-white-list-1","vabb-shw"],"host_organization":"https://openalex.org/P4310320439","host_organization_name":"IEEE Computer Society","host_organization_lineage":["https://openalex.org/P4310320439","https://openalex.org/P4310319808"],"host_organization_lineage_names":["IEEE Computer Society","Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Computer","raw_type":"journal-article"},"volume":null,"type":"article","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5025720943","display_name":"Edmund U. Cohler","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I1281412581","display_name":"Center for Science in the Public Interest (United States)","ror":"https://ror.org/00av7p167","country_code":"US","type":"nonprofit","lineage":["https://openalex.org/I1281412581"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"E.U. Cohler","raw_affiliation_strings":["CSPI, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"CSPI, USA","institution_ids":["https://openalex.org/I1281412581"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5041635521","display_name":"J.E. Storer","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I1281412581","display_name":"Center for Science in the Public Interest (United States)","ror":"https://ror.org/00av7p167","country_code":"US","type":"nonprofit","lineage":["https://openalex.org/I1281412581"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"J.E. Storer","raw_affiliation_strings":["CSPI, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"CSPI, USA","institution_ids":["https://openalex.org/I1281412581"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I1281412581"],"apc_list":{"value":2995,"currency":"USD","value_usd":2995},"apc_paid":null,"fwci":2.9133,"has_fulltext":false,"cited_by_count":26,"citation_normalized_percentile":{"value":0.89347079,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"14","issue":"9","first_page":"28","last_page":"36"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9937000274658203,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9937000274658203,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.002199999988079071,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10715","display_name":"Distributed and Parallel Computing Systems","score":0.0008999999845400453,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/task-parallelism","display_name":"task parallelism","score":0.9369999766349792},{"id":"https://openalex.org/keywords/array-processors","display_name":"array processors","score":0.9390000104904175},{"id":"https://openalex.org/keywords/parallel-architecture","display_name":"parallel architecture","score":0.8479999899864197}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8468119502067566},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6400626301765442},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.6234977841377258},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5665078163146973},{"id":"https://openalex.org/C37139622","wikidata":"https://www.wikidata.org/wiki/Q386953","display_name":"Cellular architecture","level":5,"score":0.5552129149436951},{"id":"https://openalex.org/C106515295","wikidata":"https://www.wikidata.org/wiki/Q26806595","display_name":"Parallel processing","level":2,"score":0.4119471609592438},{"id":"https://openalex.org/C55356503","wikidata":"https://www.wikidata.org/wiki/Q2136675","display_name":"Reference architecture","level":4,"score":0.31938523054122925},{"id":"https://openalex.org/C35869016","wikidata":"https://www.wikidata.org/wiki/Q846636","display_name":"Software architecture","level":3,"score":0.22964215278625488},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.19156715273857117},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.1688847541809082},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/c-m.1981.220596","doi":"https://doi.org/10.1109/c-m.1981.220596","is_oa":false,"landing_page_url":"https://doi.org/10.1109/c-m.1981.220596","pdf_url":null,"source":{"id":"https://openalex.org/S178916657","display_name":"Computer","issn_l":"0018-9162","issn":["0018-9162","1558-0814"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["anvur-class-a","anvur-scientific","cwts-core","dongbi-b","jufo-2","norway-2","poland-70","russia-white-list-1","vabb-shw"],"host_organization":"https://openalex.org/P4310320439","host_organization_name":"IEEE Computer Society","host_organization_lineage":["https://openalex.org/P4310320439","https://openalex.org/P4310319808"],"host_organization_lineage_names":["IEEE Computer Society","Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Computer","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W140492415","https://openalex.org/W57965955","https://openalex.org/W1988652250","https://openalex.org/W3101747802","https://openalex.org/W147871506","https://openalex.org/W4414937971","https://openalex.org/W2563217728","https://openalex.org/W75606983","https://openalex.org/W2297621172","https://openalex.org/W2158395626"],"abstract_inverted_index":{"Based":[0],"on":[1],"the":[2,11],"natural":[3],"division":[4],"of":[5],"mathematical":[6],"problems,":[7],"functional":[8],"parallelism":[9],"becomes":[10],"architectural":[12],"key":[13],"for":[14,18],"improving":[15],"speed/cost":[16],"ratios":[17],"array":[19],"processors.":[20]},"counts_by_year":[],"updated_date":"2026-11-10T11:39:43.021295","created_date":"2016-06-24T00:00:00"}
