{"id":"https://openalex.org/W1992206012","doi":"https://doi.org/10.1145/1465482.1465537","title":"A functional description of macromodules","display_name":"A functional description of macromodules","publication_year":1967,"publication_date":"1967-01-01","ids":{"openalex":"https://openalex.org/W1992206012","doi":"https://doi.org/10.1145/1465482.1465537","mag":"1992206012"},"language":"en","primary_location":{"id":"doi:10.1145/1465482.1465537","doi":"https://doi.org/10.1145/1465482.1465537","is_oa":true,"landing_page_url":"https://doi.org/10.1145/1465482.1465537","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/1465482.1465537","source":{"id":"https://openalex.org/S7407086511","display_name":"AFIPS Spring Joint Computer Conference (SJCC)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the April 18-20, 1967, spring joint computer conference on - AFIPS '67 (Spring)","raw_type":"proceedings-article"},"volume":null,"type":"conference-abstract","is_traditional":false,"indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"bronze","oa_url":"https://dl.acm.org/doi/pdf/10.1145/1465482.1465537","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5110034596","display_name":"Severo M. Ornstein","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I204465549","display_name":"Washington University in St. Louis","ror":"https://ror.org/01yc7t268","country_code":"US","type":"education","lineage":["https://openalex.org/I204465549"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Severo M. Ornstein","raw_affiliation_strings":["Washington University, St. Louis, Missouri"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Washington University, St. Louis, Missouri","institution_ids":["https://openalex.org/I204465549"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5067884347","display_name":"Mishell J. Stucki","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I204465549","display_name":"Washington University in St. Louis","ror":"https://ror.org/01yc7t268","country_code":"US","type":"education","lineage":["https://openalex.org/I204465549"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Mishell J. Stucki","raw_affiliation_strings":["Washington University, St. Louis, Missouri"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Washington University, St. Louis, Missouri","institution_ids":["https://openalex.org/I204465549"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5073297989","display_name":"Wesley A. Clark","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I204465549","display_name":"Washington University in St. Louis","ror":"https://ror.org/01yc7t268","country_code":"US","type":"education","lineage":["https://openalex.org/I204465549"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Wesley A. Clark","raw_affiliation_strings":["Washington University, St. Louis, Missouri"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Washington University, St. Louis, Missouri","institution_ids":["https://openalex.org/I204465549"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I204465549"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":true,"cited_by_count":36,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"337","last_page":"337"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.6269999742507935,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.6269999742507935,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.09139999747276306,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.08669999986886978,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/modular-building-blocks","display_name":"modular building blocks","score":0.6510000228881836},{"id":"https://openalex.org/keywords/control-network","display_name":"control network","score":0.3269999921321869},{"id":"https://openalex.org/keywords/control-structure-design","display_name":"control structure design","score":0.7699999809265137},{"id":"https://openalex.org/keywords/flowcharts","display_name":"flowcharts","score":0.550000011920929},{"id":"https://openalex.org/keywords/memory-modules","display_name":"memory modules","score":0.5609999895095825},{"id":"https://openalex.org/keywords/linguistic-registers","display_name":"register","score":0.5260000228881836},{"id":"https://openalex.org/keywords/adders","display_name":"adders","score":0.8370000123977661},{"id":"https://openalex.org/keywords/reconfigurable-systems","display_name":"reconfigurable systems","score":0.699999988079071}],"concepts":[{"id":"https://openalex.org/C2781089630","wikidata":"https://www.wikidata.org/wiki/Q21856745","display_name":"Realization (probability)","level":2,"score":0.7157320380210876},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6894938945770264},{"id":"https://openalex.org/C126042441","wikidata":"https://www.wikidata.org/wiki/Q1324888","display_name":"Frame (networking)","level":2,"score":0.6611560583114624},{"id":"https://openalex.org/C2780801425","wikidata":"https://www.wikidata.org/wiki/Q5164392","display_name":"Construct (python library)","level":2,"score":0.6514180898666382},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.6455597281455994},{"id":"https://openalex.org/C90805587","wikidata":"https://www.wikidata.org/wiki/Q10944557","display_name":"Word (group theory)","level":2,"score":0.6415809392929077},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.5447895526885986},{"id":"https://openalex.org/C160191386","wikidata":"https://www.wikidata.org/wiki/Q868299","display_name":"Control flow","level":2,"score":0.5407661199569702},{"id":"https://openalex.org/C35304755","wikidata":"https://www.wikidata.org/wiki/Q255362","display_name":"Wiring diagram","level":2,"score":0.5379946827888489},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.45742666721343994},{"id":"https://openalex.org/C489000","wikidata":"https://www.wikidata.org/wiki/Q747385","display_name":"Data flow diagram","level":2,"score":0.4467860460281372},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.42983952164649963},{"id":"https://openalex.org/C17500928","wikidata":"https://www.wikidata.org/wiki/Q959968","display_name":"Control system","level":2,"score":0.4204292595386505},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.3820153772830963},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.24228405952453613},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.23555442690849304},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2018875777721405},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.19756343960762024},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.19683915376663208},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.1447257399559021},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.099759042263031},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/1465482.1465537","doi":"https://doi.org/10.1145/1465482.1465537","is_oa":true,"landing_page_url":"https://doi.org/10.1145/1465482.1465537","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/1465482.1465537","source":{"id":"https://openalex.org/S7407086511","display_name":"AFIPS Spring Joint Computer Conference (SJCC)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the April 18-20, 1967, spring joint computer conference on - AFIPS '67 (Spring)","raw_type":"proceedings-article"}],"best_oa_location":{"id":"doi:10.1145/1465482.1465537","doi":"https://doi.org/10.1145/1465482.1465537","is_oa":true,"landing_page_url":"https://doi.org/10.1145/1465482.1465537","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/1465482.1465537","source":{"id":"https://openalex.org/S7407086511","display_name":"AFIPS Spring Joint Computer Conference (SJCC)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the April 18-20, 1967, spring joint computer conference on - AFIPS '67 (Spring)","raw_type":"proceedings-article"},"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320306078","display_name":"U.S. Department of Defense","ror":"https://ror.org/0447fe631"},{"id":"https://openalex.org/F4320332161","display_name":"National Institutes of Health","ror":"https://ror.org/01cwqze88"},{"id":"https://openalex.org/F4320332815","display_name":"Advanced Research Projects Agency","ror":"https://ror.org/02caytj08"}],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W1992206012.pdf","grobid_xml":"https://content.openalex.org/works/W1992206012.grobid-xml"},"referenced_works_count":2,"referenced_works":["https://openalex.org/W2086285232","https://openalex.org/W2086487975"],"related_works":["https://openalex.org/W205428449","https://openalex.org/W2086487975","https://openalex.org/W2086285232","https://openalex.org/W2089232282","https://openalex.org/W2009548258","https://openalex.org/W1988905905","https://openalex.org/W7132482572","https://openalex.org/W3032716630","https://openalex.org/W4232111633","https://openalex.org/W2057724306"],"abstract_inverted_index":{"This":[0],"paper":[1],"describes":[2],"a":[3,44,71,125,134],"set":[4],"of":[5,43,70,117,133],"macromodular":[6],"building":[7],"blocks":[8],"such":[9],"as":[10],"registers,":[11],"adders,":[12],"memories,":[13],"control":[14,58,119,122,135],"devices,":[15],"etc.,":[16],"from":[17,150],"which":[18,47],"it":[19],"is":[20,112,139],"possible":[21],"for":[22,49,124],"the":[23,39,115,131,142,146],"electronically-naive":[24],"to":[25,106,114,141,152],"construct":[26],"arbitrarily":[27],"large":[28],"and":[29,57,76,101],"complex":[30],"computers":[31],"that":[32],"work.":[33],"Machines":[34],"are":[35,60,73,90,128],"assembled":[36],"by":[37,63,92],"plugging":[38,64],"modules":[40,83,96],"into":[41],"cells":[42],"special":[45],"frame":[46],"provides":[48],"communication":[50],"between":[51],"adjacent":[52],"cells.":[53],"Explicit":[54],"data":[55],"pathways":[56],"structures":[59],"then":[61],"made":[62,157],"in":[65],"standardized":[66],"cables.":[67],"All":[68],"pieces":[69],"system":[72],"therefore":[74,155],"recoverable":[75],"systems":[77],"can":[78,102,154],"be":[79,104,156],"reconfigured":[80],"easily.":[81],"Data":[82],"process":[84,127],"twelve-bit":[85,99],"word-segments;":[86],"greater":[87],"word":[88],"lengths":[89],"obtained":[91],"interconnecting":[93],"modules.":[94],"Memory":[95],"hold":[97],"4096":[98],"segments":[100],"also":[103],"interconnected":[105],"form":[107],"larger":[108],"arrays.":[109],"Particular":[110],"attention":[111],"given":[113,126],"problem":[116],"designing":[118],"structures.":[120],"The":[121,148],"signals":[123],"routed":[129],"along":[130],"cables":[132],"network":[136],"whose":[137],"topology":[138],"isomorphic":[140],"flow":[143],"diagram":[144],"representing":[145],"process.":[147],"step":[149],"conception":[151],"realization":[153],"directly.":[158]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2018,"cited_by_count":1}],"updated_date":"2026-10-30T12:39:25.321706","created_date":"2016-06-24T00:00:00"}
