{"id":"https://openalex.org/W1978335546","doi":"https://doi.org/10.1117/12.524755","title":"Code compression for VLIW embedded processors","display_name":"Code compression for VLIW embedded processors","publication_year":2004,"publication_date":"2004-04-19","ids":{"openalex":"https://openalex.org/W1978335546","doi":"https://doi.org/10.1117/12.524755","mag":"1978335546"},"language":"en","primary_location":{"id":"doi:10.1117/12.524755","doi":"https://doi.org/10.1117/12.524755","is_oa":false,"landing_page_url":"https://doi.org/10.1117/12.524755","pdf_url":null,"source":{"id":"https://openalex.org/S183492911","display_name":"Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE","issn_l":"0277-786X","issn":["0277-786X","1996-756X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core","norway-1"],"host_organization":"https://openalex.org/P4310315543","host_organization_name":"SPIE","host_organization_lineage":["https://openalex.org/P4310315543"],"host_organization_lineage_names":["SPIE"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"SPIE Proceedings","raw_type":"proceedings-article"},"volume":null,"type":"conference-paper","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5035034751","display_name":"Emiliano Mario Piccinelli","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I4210154781","display_name":"STMicroelectronics (Italy)","ror":"https://ror.org/053bqv655","country_code":"IT","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210154781"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Emiliano Piccinelli","raw_affiliation_strings":["STMicroelectronics (Italy)"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"STMicroelectronics (Italy)","institution_ids":["https://openalex.org/I4210154781"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5067878002","display_name":"Roberto Sannino","orcid":"https://orcid.org/0000-0001-6251-4558","observed_orcids":["https://orcid.org/0000-0001-6251-4558"]},"institutions":[{"id":"https://openalex.org/I4210154781","display_name":"STMicroelectronics (Italy)","ror":"https://ror.org/053bqv655","country_code":"IT","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210154781"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Roberto Sannino","raw_affiliation_strings":["STMicroelectronics (Italy)"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"STMicroelectronics (Italy)","institution_ids":["https://openalex.org/I4210154781"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I4210154781"],"apc_list":null,"apc_paid":null,"fwci":0.2008,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.37629896,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"5309","issue":null,"first_page":"1","last_page":"1"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.8276000022888184,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.8276000022888184,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10901","display_name":"Advanced Data Compression Techniques","score":0.053599998354911804,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.045499999076128006,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/code-compression","display_name":"code compression","score":0.953000009059906},{"id":"https://openalex.org/keywords/vliw-processors","display_name":"VLIW processors","score":0.9490000009536743},{"id":"https://openalex.org/keywords/embedded-processors","display_name":"embedded processors","score":0.9589999914169312},{"id":"https://openalex.org/keywords/memory-controller","display_name":"memory controller","score":0.7379999756813049},{"id":"https://openalex.org/keywords/power-dissipation","display_name":"power dissipation","score":0.6589999794960022},{"id":"https://openalex.org/keywords/die-area","display_name":"die area","score":0.9190000295639038}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.9019860029220581},{"id":"https://openalex.org/C170595534","wikidata":"https://www.wikidata.org/wiki/Q249743","display_name":"Very long instruction word","level":2,"score":0.8182467222213745},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.5459519624710083},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.5302730798721313},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5151973366737366},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.43629974126815796},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4183552861213684},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3836830258369446},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.2950172424316406},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.14990168809890747}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1117/12.524755","doi":"https://doi.org/10.1117/12.524755","is_oa":false,"landing_page_url":"https://doi.org/10.1117/12.524755","pdf_url":null,"source":{"id":"https://openalex.org/S183492911","display_name":"Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE","issn_l":"0277-786X","issn":["0277-786X","1996-756X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core","norway-1"],"host_organization":"https://openalex.org/P4310315543","host_organization_name":"SPIE","host_organization_lineage":["https://openalex.org/P4310315543"],"host_organization_lineage_names":["SPIE"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"SPIE Proceedings","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":2,"referenced_works":["https://openalex.org/W2063678710","https://openalex.org/W2089483276"],"related_works":["https://openalex.org/W2360497714","https://openalex.org/W1572612613","https://openalex.org/W2083042011","https://openalex.org/W2126121886","https://openalex.org/W2162314586","https://openalex.org/W2149623020","https://openalex.org/W2143726022","https://openalex.org/W1798094302","https://openalex.org/W7095377043","https://openalex.org/W4238293702"],"abstract_inverted_index":{"The":[0,117],"implementation":[1,167],"of":[2,73,114,134],"processors":[3],"for":[4],"embedded":[5],"systems":[6],"implies":[7,144],"various":[8],"issues:":[9],"main":[10],"constraints":[11],"are":[12,43],"cost,":[13],"power":[14,46],"dissipation":[15],"and":[16,32,45,81,94,130],"die":[17],"area.":[18],"On":[19],"the":[20,58,71,74,85,88,104,111,115,127,131,135,139,146,152,158,169],"other":[21],"side,":[22],"new":[23,97],"terminals":[24],"perform":[25],"functions":[26],"that":[27,145],"require":[28],"more":[29],"computational":[30],"flexibility":[31],"effort.":[33],"Long":[34],"code":[35,87],"streams":[36],"must":[37],"be":[38,108,121],"loaded":[39,109],"into":[40,110,168],"memories,":[41],"which":[42],"expensive":[44],"consuming,":[47],"to":[48,107,151],"run":[49,79],"on":[50,84],"DSPs":[51],"or":[52],"CPUs.":[53],"To":[54],"overcome":[55],"this":[56,64,143],"issue,":[57],"\u201cSlimCode\u201d":[59],"proprietary":[60],"algorithm":[61],"presented":[62],"in":[63],"paper":[65],"(patent":[66],"pending":[67],"technology)":[68],"can":[69,78],"reduce":[70],"dimensions":[72],"program":[75,112],"memory.":[76],"It":[77],"offline":[80],"work":[82],"directly":[83],"binary":[86,98],"compiler":[89],"generates,":[90],"by":[91],"compressing":[92],"it":[93],"creating":[95],"a":[96,122],"file,":[99],"about":[100],"40%":[101],"smaller":[102],"than":[103],"original":[105],"one,":[106],"memory":[113],"processor.":[116],"decompression":[118],"unit":[119],"will":[120],"small":[123],"ASIC,":[124],"placed":[125],"between":[126],"Memory":[128],"Controller":[129],"System":[132],"bus":[133],"processor,":[136],"keeping":[137],"unchanged":[138],"internal":[140],"CPU":[141],"architecture:":[142],"methodology":[147],"is":[148],"completely":[149],"transparent":[150],"core.":[153,173],"We":[154],"present":[155],"comparisons":[156],"versus":[157],"state-of-the-art":[159],"IBM":[160],"Codepack":[161],"algorithm,":[162],"along":[163],"with":[164],"its":[165],"architectural":[166],"ST200":[170],"VLIW":[171],"family":[172]},"counts_by_year":[],"updated_date":"2026-10-30T12:39:25.321706","created_date":"2016-06-24T00:00:00"}