{"id":"https://openalex.org/W1973456473","doi":"https://doi.org/10.1109/40.768501","title":"Using term rewriting systems to design and verify processors","display_name":"Using term rewriting systems to design and verify processors","publication_year":1999,"publication_date":"1999-05-01","ids":{"openalex":"https://openalex.org/W1973456473","doi":"https://doi.org/10.1109/40.768501","mag":"1973456473"},"language":"en","primary_location":{"id":"doi:10.1109/40.768501","doi":"https://doi.org/10.1109/40.768501","is_oa":false,"landing_page_url":"https://doi.org/10.1109/40.768501","pdf_url":null,"source":{"id":"https://openalex.org/S59697426","display_name":"IEEE Micro","issn_l":"0272-1732","issn":["0272-1732","1937-4143"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core","dongbi-a","jufo-3","norway-2","poland-140","russia-white-list-1"],"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Micro","raw_type":"journal-article"},"volume":null,"type":"article","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5060692552","display_name":"Arvind Arvind","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I63966007","display_name":"Massachusetts Institute of Technology","ror":"https://ror.org/042nb2s44","country_code":"US","type":"education","lineage":["https://openalex.org/I63966007"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Arvind","raw_affiliation_strings":["Massachusetts Institute of Technology"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Massachusetts Institute of Technology","institution_ids":["https://openalex.org/I63966007"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101844413","display_name":"Xiaowei Shen","orcid":"https://orcid.org/0000-0002-0621-4371","observed_orcids":["https://orcid.org/0000-0002-0621-4371","https://orcid.org/0009-0002-5420-583X"]},"institutions":[{"id":"https://openalex.org/I63966007","display_name":"Massachusetts Institute of Technology","ror":"https://ror.org/042nb2s44","country_code":"US","type":"education","lineage":["https://openalex.org/I63966007"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"X. Shen","raw_affiliation_strings":["Massachusetts Institute of Technology"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Massachusetts Institute of Technology","institution_ids":["https://openalex.org/I63966007"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I63966007"],"apc_list":{"value":2995,"currency":"USD","value_usd":2995},"apc_paid":null,"fwci":7.8309,"has_fulltext":false,"cited_by_count":77,"citation_normalized_percentile":{"value":0.97111818,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":87,"max":97},"biblio":{"volume":"19","issue":"3","first_page":"36","last_page":"46"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.5547000169754028,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.5547000169754028,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.26829999685287476,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10126","display_name":"Logic, programming, and type systems","score":0.13339999318122864,"subfield":{"id":"https://openalex.org/subfields/1712","display_name":"Software"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/term-rewriting-systems","display_name":"term rewriting systems","score":1.0},{"id":"https://openalex.org/keywords/processor-design","display_name":"processor design","score":0.8629999756813049},{"id":"https://openalex.org/keywords/processor-verification","display_name":"processor verification","score":0.8629999756813049},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"high-level synthesis","score":0.8180000185966492},{"id":"https://openalex.org/keywords/speculative-execution","display_name":"speculative execution","score":0.6830000281333923},{"id":"https://openalex.org/keywords/register-renaming","display_name":"register renaming","score":0.9629999995231628},{"id":"https://openalex.org/keywords/out-of-order-execution","display_name":"out-of-order execution","score":1.0},{"id":"https://openalex.org/keywords/microarchitecture","display_name":"microarchitecture","score":0.527999997138977},{"id":"https://openalex.org/keywords/architectural-exploration","display_name":"architecture exploration","score":0.7860000133514404},{"id":"https://openalex.org/keywords/write-buffer","display_name":"write buffer","score":0.7450000047683716},{"id":"https://openalex.org/keywords/cache","display_name":"cache memory","score":0.9070000052452087},{"id":"https://openalex.org/keywords/multiprocessor-systems","display_name":"multiprocessor systems","score":0.8420000076293945},{"id":"https://openalex.org/keywords/behavioral-equivalence","display_name":"behavioral equivalence","score":0.36500000953674316}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.9110598564147949},{"id":"https://openalex.org/C154690210","wikidata":"https://www.wikidata.org/wiki/Q1668499","display_name":"Rewriting","level":2,"score":0.6785316467285156},{"id":"https://openalex.org/C55439883","wikidata":"https://www.wikidata.org/wiki/Q360812","display_name":"Correctness","level":2,"score":0.6495256423950195},{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.6197967529296875},{"id":"https://openalex.org/C61797465","wikidata":"https://www.wikidata.org/wiki/Q1188986","display_name":"Term (time)","level":2,"score":0.5677971243858337},{"id":"https://openalex.org/C4822641","wikidata":"https://www.wikidata.org/wiki/Q846651","display_name":"Multiprocessing","level":2,"score":0.5168100595474243},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.4747267961502075},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.43158864974975586},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.38996821641921997},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3754497170448303},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3630792498588562},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/40.768501","doi":"https://doi.org/10.1109/40.768501","is_oa":false,"landing_page_url":"https://doi.org/10.1109/40.768501","pdf_url":null,"source":{"id":"https://openalex.org/S59697426","display_name":"IEEE Micro","issn_l":"0272-1732","issn":["0272-1732","1937-4143"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core","dongbi-a","jufo-3","norway-2","poland-140","russia-white-list-1"],"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Micro","raw_type":"journal-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.31.2833","doi":null,"is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.31.2833","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.csg.lcs.mit.edu/Users/xwshen/papers/memo419.ps","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320306078","display_name":"U.S. Department of Defense","ror":"https://ror.org/0447fe631"},{"id":"https://openalex.org/F4320332815","display_name":"Advanced Research Projects Agency","ror":"https://ror.org/02caytj08"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1500286044","https://openalex.org/W1538592187","https://openalex.org/W1555915743","https://openalex.org/W1583295953","https://openalex.org/W1683919907","https://openalex.org/W1741528175","https://openalex.org/W2066689215","https://openalex.org/W2097931542","https://openalex.org/W2103709633","https://openalex.org/W2725179571","https://openalex.org/W4238416552","https://openalex.org/W4388310154"],"related_works":["https://openalex.org/W7099233857","https://openalex.org/W1683919907","https://openalex.org/W7099338558","https://openalex.org/W7095352629","https://openalex.org/W32166614","https://openalex.org/W7098584355","https://openalex.org/W7056090194","https://openalex.org/W7095366599","https://openalex.org/W2167747215","https://openalex.org/W7095682679"],"abstract_inverted_index":{"Term":[0],"rewriting":[1],"systems":[2,13],"(TRSs)":[3],"offer":[4],"a":[5,22,57,77,92,122],"convenient":[6],"way":[7],"to":[8,21,75,90,98,103],"describe":[9,76],"parallel":[10],"and":[11,14,50,62,84],"asynchronous":[12],"prove":[15],"an":[16],"implementation's":[17],"correctness":[18],"with":[19,27],"respect":[20],"specification.":[23],"TRS":[24],"descriptions,":[25],"augmented":[26],"proper":[28],"information":[29],"about":[30],"the":[31,37,60,100,116,147],"system":[32],"building":[33],"blocks,":[34],"also":[35],"hold":[36],"promise":[38],"of":[39,59,81,119,128,141,149],"high-level":[40],"synthesis.":[41],"High-level":[42],"architectural":[43,54],"descriptions":[44,127,143],"that":[45,111],"are":[46,130],"both":[47],"automatically":[48],"synthesizable":[49],"verifiable":[51],"would":[52],"permit":[53],"exploration":[55],"at":[56],"fraction":[58],"time":[61],"cost":[63],"required":[64],"by":[65],"current":[66],"commercial":[67],"tools.":[68],"In":[69],"this":[70],"article,":[71],"we":[72,109],"use":[73],"TRSs":[74,96],"speculative":[78,113],"processor":[79,114],"capable":[80],"register":[82],"renaming":[83],"out-of-order":[85],"execution.":[86],"We":[87],"lack":[88],"space":[89],"discuss":[91],"synthesis":[93,106],"procedure":[94],"from":[95],"or":[97,155],"provide":[99],"details":[101],"needed":[102],"make":[104],"automatic":[105],"feasible;":[107],"Nevertheless,":[108],"show":[110],"our":[112],"produces":[115],"same":[117],"set":[118],"behaviors":[120],"as":[121,152],"simple":[123],"nonpipelined":[124],"implementation.":[125],"Our":[126],"microarchitectures":[129],"more":[131],"precise":[132],"than":[133],"those":[134],"found":[135],"in":[136,158],"modern":[137],"textbooks.":[138],"The":[139],"clarity":[140],"these":[142],"lets":[144],"us":[145],"study":[146],"impact":[148],"features":[150],"such":[151],"write":[153],"buffers":[154],"caches,":[156],"especially":[157],"multiprocessor":[159],"systems.":[160]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":2},{"year":2015,"cited_by_count":1},{"year":2013,"cited_by_count":4},{"year":2012,"cited_by_count":1}],"updated_date":"2026-11-12T12:28:57.059296","created_date":"2016-06-24T00:00:00"}