{"id":"https://openalex.org/W197042351","doi":null,"title":"A parallel partitioning algorithm for parallel reconfigurable computing","display_name":"A parallel partitioning algorithm for parallel reconfigurable computing","publication_year":2007,"publication_date":"2007-07-09","ids":{"openalex":"https://openalex.org/W197042351","mag":"197042351"},"language":"en","primary_location":{"id":"mag:197042351","doi":null,"is_oa":false,"landing_page_url":"http://dl.acm.org/citation.cfm?id=1659793","pdf_url":null,"source":{"id":"https://openalex.org/S4306419187","display_name":"International Conference on Circuits","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":"International Conference on Circuits","raw_type":null},"volume":null,"type":"conference-paper","is_traditional":true,"indexed_in":[],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5033495885","display_name":"Yung-Chuan Jiang","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I91807558","display_name":"National Cheng Kung University","ror":"https://ror.org/01b8kcc49","country_code":"TW","type":"education","lineage":["https://openalex.org/I91807558"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Yung-Chuan Jiang","raw_affiliation_strings":["National Cheng Kung University, Tainan,  Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"National Cheng Kung University, Tainan,  Taiwan","institution_ids":["https://openalex.org/I91807558"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5112046582","display_name":"Yen\u2010Tai Lai","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I91807558","display_name":"National Cheng Kung University","ror":"https://ror.org/01b8kcc49","country_code":"TW","type":"education","lineage":["https://openalex.org/I91807558"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Yen\u2010Tai Lai","raw_affiliation_strings":["National Cheng Kung University, Tainan,  Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"National Cheng Kung University, Tainan,  Taiwan","institution_ids":["https://openalex.org/I91807558"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I91807558"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.0,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"146","last_page":"151"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9926999807357788,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9926999807357788,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.00559999980032444,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.00019999999494757503,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"reconfigurable computing","score":0.8949999809265137},{"id":"https://openalex.org/keywords/fpga","display_name":"FPGA","score":0.6389999985694885},{"id":"https://openalex.org/keywords/dynamic-reconfiguration","display_name":"dynamic reconfiguration","score":0.7940000295639038},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"high-level synthesis","score":0.8379999995231628},{"id":"https://openalex.org/keywords/directed-acyclic-graphs","display_name":"directed acyclic graphs","score":0.7450000047683716},{"id":"https://openalex.org/keywords/execution-time-reduction","display_name":"execution time reduction","score":0.8500000238418579},{"id":"https://openalex.org/keywords/application-performance","display_name":"application performance","score":0.5630000233650208},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"parallel computing","score":0.5899999737739563}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8242206573486328},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.7898364067077637},{"id":"https://openalex.org/C120373497","wikidata":"https://www.wikidata.org/wiki/Q1087987","display_name":"Parallel algorithm","level":2,"score":0.5796632170677185},{"id":"https://openalex.org/C106515295","wikidata":"https://www.wikidata.org/wiki/Q26806595","display_name":"Parallel processing","level":2,"score":0.5218566656112671},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.5010890960693359},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.4993774890899658},{"id":"https://openalex.org/C51823790","wikidata":"https://www.wikidata.org/wiki/Q504353","display_name":"Greedy algorithm","level":2,"score":0.4941883385181427},{"id":"https://openalex.org/C132525143","wikidata":"https://www.wikidata.org/wiki/Q141488","display_name":"Graph","level":2,"score":0.47337621450424194},{"id":"https://openalex.org/C74197172","wikidata":"https://www.wikidata.org/wiki/Q1195339","display_name":"Directed acyclic graph","level":2,"score":0.44817036390304565},{"id":"https://openalex.org/C2985918086","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel architecture","level":3,"score":0.44640302658081055},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.4442238211631775},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.19671106338500977},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.14434528350830078},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"mag:197042351","doi":null,"is_oa":false,"landing_page_url":"http://dl.acm.org/citation.cfm?id=1659793","pdf_url":null,"source":{"id":"https://openalex.org/S4306419187","display_name":"International Conference on Circuits","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":"International Conference on Circuits","raw_type":null}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W583394863","https://openalex.org/W1484423943","https://openalex.org/W1544057354","https://openalex.org/W1972104583","https://openalex.org/W2011039300","https://openalex.org/W2021146421","https://openalex.org/W2100304552","https://openalex.org/W2103436822","https://openalex.org/W2105815873","https://openalex.org/W2112732048","https://openalex.org/W2115512913","https://openalex.org/W2135050419","https://openalex.org/W2136539269","https://openalex.org/W2155814884","https://openalex.org/W2160651385","https://openalex.org/W2160741620","https://openalex.org/W2164939754","https://openalex.org/W2477064431"],"related_works":["https://openalex.org/W2105811127","https://openalex.org/W2039871026","https://openalex.org/W2022386909","https://openalex.org/W1603653058","https://openalex.org/W1998879565","https://openalex.org/W2045100197","https://openalex.org/W2029849575","https://openalex.org/W2351595050","https://openalex.org/W7067647069","https://openalex.org/W1979297580"],"abstract_inverted_index":{"A":[0,27,56],"parallel":[1,21,41],"processing":[2,22,42],"reconfigurable":[3,13],"architecture":[4,17,36],"consists":[5],"of":[6],"multiple":[7],"processor":[8],"elements":[9],"as":[10],"FPGAs.":[11],"Dynamically":[12],"computing":[14],"in":[15,94],"the":[16,35,68,78,83,95],"combines":[18],"with":[19],"a":[20,63,70],"technique":[23],"for":[24],"high-level":[25],"synthesis.":[26],"new":[28],"partitioning":[29],"algorithm":[30,48,69,88],"is":[31,60,72,92],"presented":[32],"based":[33],"on":[34],"and":[37,81,90],"needs":[38],"to":[39,52],"consider":[40],"different":[43],"from":[44],"transitional":[45],"partitioning.":[46],"The":[47],"minimizes":[49],"execution":[50],"time":[51],"maximize":[53],"application":[54,59],"performance.":[55],"program":[57],"or":[58],"represented":[61],"by":[62,76],"directed":[64],"acyclic":[65],"graph.":[66],"In":[67],"graph":[71],"divided":[73],"into":[74],"subgraphs":[75],"applying":[77],"greedy":[79],"method":[80],"obtains":[82],"minimizing":[84],"depth":[85],"solution.":[86],"Our":[87],"efficiency":[89],"effectiveness":[91],"shown":[93],"results.":[96]},"counts_by_year":[],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2016-06-24T00:00:00"}