{"id":"https://openalex.org/W1970116248","doi":"https://doi.org/10.1109/isscc.1993.280032","title":"Real-time reconfigurable logic circuits using neuron MOS transistors","display_name":"Real-time reconfigurable logic circuits using neuron MOS transistors","publication_year":1993,"publication_date":"1993-01-01","ids":{"openalex":"https://openalex.org/W1970116248","doi":"https://doi.org/10.1109/isscc.1993.280032","mag":"1970116248"},"language":"en","primary_location":{"id":"doi:10.1109/isscc.1993.280032","doi":"https://doi.org/10.1109/isscc.1993.280032","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc.1993.280032","pdf_url":null,"source":{"id":"https://openalex.org/S4210210374","display_name":"Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference","issn_l":"0193-6530","issn":["0193-6530","2376-8606"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core","norway-1"],"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"1993 IEEE International Solid-State Circuits Conference Digest of Technical Papers","raw_type":"proceedings-article"},"volume":null,"type":"conference-paper","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5111934278","display_name":"T. Shibata","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I201537933","display_name":"Tohoku University","ror":"https://ror.org/01dq60k83","country_code":"JP","type":"education","lineage":["https://openalex.org/I201537933"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"T. Shibata","raw_affiliation_strings":["University of Tohoku, Sendai, Japan","Thoku Univ., Sendai, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Tohoku, Sendai, Japan","institution_ids":["https://openalex.org/I201537933"]},{"raw_affiliation_string":"Thoku Univ., Sendai, Japan","institution_ids":["https://openalex.org/I201537933"]}]},{"author_position":"middle","author":{"id":null,"display_name":"K. Kotani","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I201537933","display_name":"Tohoku University","ror":"https://ror.org/01dq60k83","country_code":"JP","type":"education","lineage":["https://openalex.org/I201537933"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"K. Kotani","raw_affiliation_strings":["University of Tohoku, Sendai, Japan","Thoku Univ., Sendai, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Tohoku, Sendai, Japan","institution_ids":["https://openalex.org/I201537933"]},{"raw_affiliation_string":"Thoku Univ., Sendai, Japan","institution_ids":["https://openalex.org/I201537933"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5110826182","display_name":"T. Ohmi","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I201537933","display_name":"Tohoku University","ror":"https://ror.org/01dq60k83","country_code":"JP","type":"education","lineage":["https://openalex.org/I201537933"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"T. Ohmi","raw_affiliation_strings":["University of Tohoku, Sendai, Japan","Thoku Univ., Sendai, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Tohoku, Sendai, Japan","institution_ids":["https://openalex.org/I201537933"]},{"raw_affiliation_string":"Thoku Univ., Sendai, Japan","institution_ids":["https://openalex.org/I201537933"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I201537933"],"apc_list":null,"apc_paid":null,"fwci":10.0586,"has_fulltext":false,"cited_by_count":37,"citation_normalized_percentile":{"value":0.98481793,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"238","last_page":"239"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.8637999892234802,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.8637999892234802,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.03709999844431877,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.03579999879002571,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/reconfigurable-logic-circuits","display_name":"reconfigurable logic circuits","score":0.843999981880188},{"id":"https://openalex.org/keywords/cmos-logic-gates","display_name":"CMOS logic gates","score":0.5559999942779541},{"id":"https://openalex.org/keywords/neuromorphic-hardware","display_name":"neuromorphic hardware","score":0.47099998593330383}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6341947317123413},{"id":"https://openalex.org/C124296912","wikidata":"https://www.wikidata.org/wiki/Q575178","display_name":"NAND gate","level":3,"score":0.5900712013244629},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5876457095146179},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5789971351623535},{"id":"https://openalex.org/C7234692","wikidata":"https://www.wikidata.org/wiki/Q4116068","display_name":"NAND logic","level":4,"score":0.5742905139923096},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5364120602607727},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.49877190589904785},{"id":"https://openalex.org/C165862026","wikidata":"https://www.wikidata.org/wiki/Q670372","display_name":"NOR logic","level":5,"score":0.469228595495224},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.4478064477443695},{"id":"https://openalex.org/C130126468","wikidata":"https://www.wikidata.org/wiki/Q4652943","display_name":"AND-OR-Invert","level":5,"score":0.43567219376564026},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4200219511985779},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4128114581108093},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.36518561840057373},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.3235727548599243},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.27086523175239563},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.256125807762146},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.1840054988861084},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1704169511795044},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.1046040952205658},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isscc.1993.280032","doi":"https://doi.org/10.1109/isscc.1993.280032","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc.1993.280032","pdf_url":null,"source":{"id":"https://openalex.org/S4210210374","display_name":"Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference","issn_l":"0193-6530","issn":["0193-6530","2376-8606"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core","norway-1"],"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"1993 IEEE International Solid-State Circuits Conference Digest of Technical Papers","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":3,"referenced_works":["https://openalex.org/W2160142098","https://openalex.org/W2545117335","https://openalex.org/W2545311598"],"related_works":["https://openalex.org/W1983051814","https://openalex.org/W2142659398","https://openalex.org/W1998847131","https://openalex.org/W7095150074","https://openalex.org/W1566416706","https://openalex.org/W2074260540","https://openalex.org/W2257332036","https://openalex.org/W7146821184","https://openalex.org/W2545117335","https://openalex.org/W2585034602"],"abstract_inverted_index":{"A":[0],"highly-flexible":[1],"real-time-reconfigurable":[2],"logic":[3,17,22],"circuit":[4,46,97,115],"implemented":[5],"using":[6,79],"a":[7,57,69,84,112],"regular":[8],"CMOS":[9,87],"process":[10],"is":[11,47,111],"presented.":[12,104],"The":[13,45,72],"circuit,":[14],"called":[15],"soft-hardware":[16],"(SHL),":[18],"can":[19],"alter":[20],"its":[21],"function":[23,64],"(e.g.":[24],"AND,":[25],"OR,":[26,30],"NAND,":[27],"NOR,":[28],"Exclusive":[29,31],"NOR)":[32],"in":[33,116],"real":[34],"time":[35],"according":[36],"to":[37],"external":[38],"control":[39],"signals":[40],"with":[41],"no":[42],"hardware":[43],"modification.":[44],"one":[48],"application":[49],"of":[50,65,94,107],"the":[51,63,91,95],"neuron":[52],"MOSFET":[53],"(neuMOS":[54],"or":[55],"vMOS),":[56],"multiple-input":[58],"functional":[59],"MOS":[60],"transistor":[61],"simulating":[62],"biological":[66],"neurons":[67],"by":[68,77,83,129],"single":[70],"device.":[71],"concept":[73,110],"has":[74,126],"been":[75,127],"verified":[76,128],"experiments":[78],"test":[80],"circuits":[81],"fabricated":[82],"standard":[85],"double-polysilicon":[86],"process.":[88],"Details":[89],"on":[90],"operational":[92],"principle":[93],"SHL":[96],"as":[98,100],"well":[99],"design":[101],"techniques":[102],"are":[103,122],"One":[105],"extension":[106],"this":[108],"vMOS":[109],"dynamic":[113],"data-matching":[114],"which":[117],"rules":[118],"for":[119],"data":[120],"matching":[121],"time-variable.":[123],"Circuit":[124],"operation":[125],"experiments.>":[130]},"counts_by_year":[],"updated_date":"2026-10-06T10:28:23.643775","created_date":"2016-06-24T00:00:00"}