{"id":"https://openalex.org/W1960026154","doi":"https://doi.org/10.1109/vlsit.2001.934953","title":"Impact of CMOS process scaling and SOI on the soft error rates of logic processes","display_name":"Impact of CMOS process scaling and SOI on the soft error rates of logic processes","publication_year":2002,"publication_date":"2002-11-13","ids":{"openalex":"https://openalex.org/W1960026154","doi":"https://doi.org/10.1109/vlsit.2001.934953","mag":"1960026154"},"language":"en","primary_location":{"id":"doi:10.1109/vlsit.2001.934953","doi":"https://doi.org/10.1109/vlsit.2001.934953","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsit.2001.934953","pdf_url":null,"source":{"id":"https://openalex.org/S4306421008","display_name":"Symposium on VLSI Technology","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)","raw_type":"proceedings-article"},"volume":null,"type":"conference-paper","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5064605937","display_name":"Scott A. Hareland","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"S. Hareland","raw_affiliation_strings":["Logic Technology Development, Intel Corporation, Hillsboro, OR, USA","Intel Corporation, , Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Logic Technology Development, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, , Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5040973208","display_name":"Jose A. Maiz","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"J. Maiz","raw_affiliation_strings":["Logic Technology Development, Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Logic Technology Development, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5015344981","display_name":"M. Alavi","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"M. Alavi","raw_affiliation_strings":["Logic Technology Development, Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Logic Technology Development, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5043092503","display_name":"K. Mistry","orcid":"https://orcid.org/0000-0001-6472-599X","observed_orcids":["https://orcid.org/0000-0001-6472-599X"]},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"K. Mistry","raw_affiliation_strings":["Logic Technology Development, Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Logic Technology Development, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5014528235","display_name":"S. Walsta","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"S. Walsta","raw_affiliation_strings":["Logic Technology Development, Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Logic Technology Development, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5082987137","display_name":"Changhong Dai","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Changhong Dai","raw_affiliation_strings":["Logic Technology Development, Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Logic Technology Development, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":13.8917,"has_fulltext":false,"cited_by_count":124,"citation_normalized_percentile":{"value":0.99461354,"is_in_top_1_percent":true,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":88,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"73","last_page":"74"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.00019999999494757503,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/soft-error-rate","display_name":"soft error rate","score":0.9950000047683716},{"id":"https://openalex.org/keywords/cmos-scaling","display_name":"CMOS scaling","score":0.8560000061988831},{"id":"https://openalex.org/keywords/silicon-on-insulator","display_name":"silicon-on-insulator","score":0.9300000071525574},{"id":"https://openalex.org/keywords/logic-circuits","display_name":"logic circuits","score":0.5699999928474426},{"id":"https://openalex.org/keywords/alpha-radiation","display_name":"alpha radiation","score":0.49300000071525574},{"id":"https://openalex.org/keywords/neutron-radiation","display_name":"neutron radiation","score":0.6779999732971191},{"id":"https://openalex.org/keywords/cache","display_name":"cache memory","score":0.4050000011920929},{"id":"https://openalex.org/keywords/radiation-hardness","display_name":"radioresistance","score":0.44600000977516174},{"id":"https://openalex.org/keywords/technology-generation","display_name":"technology generation","score":0.5}],"concepts":[{"id":"https://openalex.org/C154474529","wikidata":"https://www.wikidata.org/wiki/Q1658917","display_name":"Soft error","level":2,"score":0.7321906685829163},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.6611443161964417},{"id":"https://openalex.org/C62611344","wikidata":"https://www.wikidata.org/wiki/Q1062658","display_name":"Node (physics)","level":2,"score":0.648088812828064},{"id":"https://openalex.org/C99844830","wikidata":"https://www.wikidata.org/wiki/Q102441924","display_name":"Scaling","level":2,"score":0.616395890712738},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.577907383441925},{"id":"https://openalex.org/C53143962","wikidata":"https://www.wikidata.org/wiki/Q1478788","display_name":"Silicon on insulator","level":3,"score":0.5398440361022949},{"id":"https://openalex.org/C93389723","wikidata":"https://www.wikidata.org/wiki/Q7247313","display_name":"Process variation","level":3,"score":0.5290205478668213},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.510767936706543},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.48573070764541626},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.48086434602737427},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.46396008133888245},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.46265465021133423},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4561864137649536},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.43675529956817627},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.31015831232070923},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.27247995138168335},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.27229130268096924},{"id":"https://openalex.org/C49040817","wikidata":"https://www.wikidata.org/wiki/Q193091","display_name":"Optoelectronics","level":1,"score":0.2320287525653839},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.22536736726760864},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.21992692351341248},{"id":"https://openalex.org/C544956773","wikidata":"https://www.wikidata.org/wiki/Q670","display_name":"Silicon","level":2,"score":0.15565025806427002},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.1431007981300354},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.09271612763404846},{"id":"https://openalex.org/C66938386","wikidata":"https://www.wikidata.org/wiki/Q633538","display_name":"Structural engineering","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vlsit.2001.934953","doi":"https://doi.org/10.1109/vlsit.2001.934953","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsit.2001.934953","pdf_url":null,"source":{"id":"https://openalex.org/S4306421008","display_name":"Symposium on VLSI Technology","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320338304","display_name":"Los Alamos National Laboratory","ror":"https://ror.org/01e41cf67"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":2,"referenced_works":["https://openalex.org/W2131764298","https://openalex.org/W2270454042"],"related_works":["https://openalex.org/W1564617507","https://openalex.org/W2544676522","https://openalex.org/W7099454688","https://openalex.org/W7098245798","https://openalex.org/W2169213530","https://openalex.org/W1993206924","https://openalex.org/W2148019367","https://openalex.org/W2139004760","https://openalex.org/W2142358791","https://openalex.org/W1993013098"],"abstract_inverted_index":{"Technology":[0],"scaling,":[1],"reduction":[2,31],"in":[3,9,32,44],"operating":[4],"voltages,":[5],"and":[6,12,39,75],"the":[7,21,33,59,84,103],"increase":[8],"cache":[10,40],"size":[11],"circuit":[13,37],"complexity":[14],"have":[15,94],"been":[16,95],"key":[17],"enablers":[18],"to":[19,101],"achieving":[20],"performance":[22],"improvement":[23],"expectation":[24],"dictated":[25],"by":[26],"Moore's":[27],"Law.":[28],"The":[29],"resulting":[30],"node":[34],"charge":[35],"of":[36,62,80,105],"latches":[38],"cells":[41],"has":[42],"resulted":[43],"an":[45,77],"ever":[46],"increasing":[47],"soft":[48],"error":[49],"rate":[50],"(SER)":[51],"estimation":[52],"for":[53,83],"logic":[54],"components.":[55],"This":[56],"paper":[57],"reports":[58],"SER":[60,88,104],"impact":[61],"process":[63],"scaling":[64],"over":[65],"four":[66],"technology":[67],"generations":[68],"(0.35,":[69],"0.25,":[70],"0.18,":[71],"0.13":[72],"/spl":[73],"mu/m)":[74],"provides":[76],"experimental":[78],"assessment":[79],"alpha":[81],"and,":[82],"first":[85],"time,":[86],"neutron":[87],"on":[89],"advanced":[90,106],"SOI":[91],"processes,":[92],"which":[93],"considered":[96],"as":[97],"a":[98],"possible":[99],"method":[100],"reduce":[102],"technologies.":[107]},"counts_by_year":[{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":2},{"year":2017,"cited_by_count":3},{"year":2016,"cited_by_count":4},{"year":2015,"cited_by_count":6},{"year":2014,"cited_by_count":4},{"year":2013,"cited_by_count":3},{"year":2012,"cited_by_count":6}],"updated_date":"2026-11-03T10:50:19.383937","created_date":"2016-06-24T00:00:00"}
