{"id":"https://openalex.org/W1925000611","doi":"https://doi.org/10.1109/vtest.2000.843826","title":"Timing analysis of combinational circuits including capacitive coupling and statistical process variation","display_name":"Timing analysis of combinational circuits including capacitive coupling and statistical process variation","publication_year":2002,"publication_date":"2002-11-07","ids":{"openalex":"https://openalex.org/W1925000611","doi":"https://doi.org/10.1109/vtest.2000.843826","mag":"1925000611"},"language":"en","primary_location":{"id":"doi:10.1109/vtest.2000.843826","doi":"https://doi.org/10.1109/vtest.2000.843826","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vtest.2000.843826","pdf_url":null,"source":{"id":"https://openalex.org/S4210180668","display_name":"IEEE VLSI Test Symposium (VTS)","issn_l":"1093-0167","issn":["1093-0167","2375-1053"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core","jufo-1","norway-1"],"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings 18th IEEE VLSI Test Symposium","raw_type":"proceedings-article"},"volume":null,"type":"conference-paper","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":null,"display_name":"B. Choi","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"B. Choi","raw_affiliation_strings":["Intel Corporation, Chandler, AZ, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Chandler, AZ, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5027337337","display_name":"D.M.H. Walker","orcid":"https://orcid.org/0000-0002-4839-3830","observed_orcids":["https://orcid.org/0000-0002-4839-3830"]},"institutions":[{"id":"https://openalex.org/I91045830","display_name":"Texas A&M University","ror":"https://ror.org/01f5ytq51","country_code":"US","type":"education","lineage":["https://openalex.org/I91045830"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"D.M.H. Walker","raw_affiliation_strings":["Departmentof Computer Science, Texas A and M University, College Station, TX, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Departmentof Computer Science, Texas A and M University, College Station, TX, USA","institution_ids":["https://openalex.org/I91045830"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":5.2563,"has_fulltext":false,"cited_by_count":29,"citation_normalized_percentile":{"value":0.96583854,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":88,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"49","last_page":"54"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9599999785423279,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9599999785423279,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.014600000344216824,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.004699999932199717,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/timing-analysis","display_name":"timing analysis","score":0.7620000243186951},{"id":"https://openalex.org/keywords/combinational-circuits","display_name":"combinational circuits","score":0.9660000205039978},{"id":"https://openalex.org/keywords/capacitive-coupling","display_name":"capacitive coupling","score":0.9900000095367432},{"id":"https://openalex.org/keywords/statistical-process-variation","display_name":"statistical process variation","score":0.8830000162124634},{"id":"https://openalex.org/keywords/interconnect-parasitics","display_name":"interconnect parasitics","score":0.6660000085830688},{"id":"https://openalex.org/keywords/worst-case-delay","display_name":"worst-case delay","score":0.593999981880188},{"id":"https://openalex.org/keywords/input-vector-selection","display_name":"input vector selection","score":0.4399999976158142},{"id":"https://openalex.org/keywords/deep-submicron-circuits","display_name":"deep submicron circuits","score":0.8270000219345093}],"concepts":[{"id":"https://openalex.org/C93389723","wikidata":"https://www.wikidata.org/wiki/Q7247313","display_name":"Process variation","level":3,"score":0.726652979850769},{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.6895314455032349},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.6382790207862854},{"id":"https://openalex.org/C68278764","wikidata":"https://www.wikidata.org/wiki/Q444167","display_name":"Capacitive coupling","level":3,"score":0.608718752861023},{"id":"https://openalex.org/C131584629","wikidata":"https://www.wikidata.org/wiki/Q4308705","display_name":"Coupling (piping)","level":2,"score":0.6032885909080505},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.601069986820221},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5710659027099609},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.5541316270828247},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5207979083061218},{"id":"https://openalex.org/C206755178","wikidata":"https://www.wikidata.org/wiki/Q1131271","display_name":"Capacitive sensing","level":2,"score":0.4546830654144287},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4496024250984192},{"id":"https://openalex.org/C174086752","wikidata":"https://www.wikidata.org/wiki/Q5253471","display_name":"Delay calculation","level":3,"score":0.4488235414028168},{"id":"https://openalex.org/C2778334786","wikidata":"https://www.wikidata.org/wiki/Q1586270","display_name":"Variation (astronomy)","level":2,"score":0.4469418525695801},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3838993310928345},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.37937524914741516},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.19021224975585938},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.13575777411460876},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1322213113307953},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C44870925","wikidata":"https://www.wikidata.org/wiki/Q37547","display_name":"Astrophysics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vtest.2000.843826","doi":"https://doi.org/10.1109/vtest.2000.843826","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vtest.2000.843826","pdf_url":null,"source":{"id":"https://openalex.org/S4210180668","display_name":"IEEE VLSI Test Symposium (VTS)","issn_l":"1093-0167","issn":["1093-0167","2375-1053"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core","jufo-1","norway-1"],"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings 18th IEEE VLSI Test Symposium","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":31,"referenced_works":["https://openalex.org/W20194458","https://openalex.org/W1512404515","https://openalex.org/W1556480701","https://openalex.org/W1930731203","https://openalex.org/W2012426329","https://openalex.org/W2042714121","https://openalex.org/W2098706146","https://openalex.org/W2099555625","https://openalex.org/W2100196964","https://openalex.org/W2100783269","https://openalex.org/W2101572961","https://openalex.org/W2104564222","https://openalex.org/W2104805914","https://openalex.org/W2126324865","https://openalex.org/W2126827022","https://openalex.org/W2128623670","https://openalex.org/W2140823559","https://openalex.org/W2148965114","https://openalex.org/W2149335103","https://openalex.org/W2150382568","https://openalex.org/W2167232152","https://openalex.org/W2169475699","https://openalex.org/W2170625533","https://openalex.org/W2171562970","https://openalex.org/W2173124859","https://openalex.org/W3143002681","https://openalex.org/W4246830553","https://openalex.org/W4249277001","https://openalex.org/W6630663818","https://openalex.org/W6640360771","https://openalex.org/W6674918397"],"related_works":["https://openalex.org/W7098616154","https://openalex.org/W2172214102","https://openalex.org/W4254506919","https://openalex.org/W7096335943","https://openalex.org/W2139227365","https://openalex.org/W2080533153","https://openalex.org/W2120177652","https://openalex.org/W4240153331","https://openalex.org/W2139618769","https://openalex.org/W2117953147"],"abstract_inverted_index":{"Capacitive":[0],"coupling":[1],"between":[2],"interconnects":[3],"can":[4],"lead":[5],"to":[6,70],"pattern-dependent":[7],"delay":[8,65,87],"variation.":[9,93],"Statistical":[10],"process":[11],"fluctuations":[12],"result":[13],"in":[14,16,29],"variation":[15,88],"gate":[17,86],"and":[18,21,62,75,89],"interconnect":[19,22,91],"delays,":[20],"coupling.":[23,72],"These":[24],"effects":[25,48],"become":[26],"increasingly":[27],"important":[28],"deep":[30],"submicron":[31],"circuits.":[32,105],"In":[33],"this":[34],"work":[35],"we":[36],"describe":[37],"a":[38,100],"statistical":[39],"timing":[40,77,96],"analyzer":[41],"for":[42,54],"combinational":[43],"circuits":[44],"that":[45,57],"takes":[46],"these":[47,67],"into":[49],"account.":[50],"The":[51,73],"tool":[52],"searches":[53],"input":[55],"vectors":[56],"sensitize":[58],"the":[59,64,79,103],"longest":[60],"path":[61],"maximizes":[63],"on":[66,78,99],"paths":[68,80],"due":[69],"capacitive":[71],"best":[74],"worst-case":[76],"is":[81],"then":[82],"computed":[83],"using":[84],"random":[85],"spatially-correlated":[90],"parasitic":[92],"We":[94],"demonstrate":[95],"analysis":[97],"results":[98],"subset":[101],"of":[102],"ISCAS85":[104]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":2}],"updated_date":"2026-11-04T10:54:05.112534","created_date":"2016-06-24T00:00:00"}
