{"id":"https://openalex.org/W1850310409","doi":"https://doi.org/10.1109/apasic.1999.824096","title":"Pattern generation for verification of VHDL behavioral-level design","display_name":"Pattern generation for verification of VHDL behavioral-level design","publication_year":2003,"publication_date":"2003-01-22","ids":{"openalex":"https://openalex.org/W1850310409","doi":"https://doi.org/10.1109/apasic.1999.824096","mag":"1850310409"},"language":"en","primary_location":{"id":"doi:10.1109/apasic.1999.824096","doi":"https://doi.org/10.1109/apasic.1999.824096","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apasic.1999.824096","pdf_url":null,"source":{"id":"https://openalex.org/S4306502575","display_name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","raw_type":"proceedings-article"},"volume":null,"type":"conference-paper","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5007513803","display_name":"Jong-Hyeon Kim","orcid":"https://orcid.org/0000-0002-6133-1044","observed_orcids":["https://orcid.org/0000-0002-6133-1044"]},"institutions":[{"id":"https://openalex.org/I161024014","display_name":"Kwangwoon University","ror":"https://ror.org/02e9zc863","country_code":"KR","type":"education","lineage":["https://openalex.org/I161024014"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Jong-Hyeon Kim","raw_affiliation_strings":["Department of Electronic Materials Engineering, Kwangwoon University, Seoul, South Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronic Materials Engineering, Kwangwoon University, Seoul, South Korea","institution_ids":["https://openalex.org/I161024014"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5072492163","display_name":"Seung-Kyu Park","orcid":"https://orcid.org/0000-0001-7432-2844","observed_orcids":["https://orcid.org/0000-0001-7432-2844"]},"institutions":[{"id":"https://openalex.org/I161024014","display_name":"Kwangwoon University","ror":"https://ror.org/02e9zc863","country_code":"KR","type":"education","lineage":["https://openalex.org/I161024014"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Seung-Kyu Park","raw_affiliation_strings":["Department of Electronic Materials Engineering, Kwangwoon University, Seoul, South Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronic Materials Engineering, Kwangwoon University, Seoul, South Korea","institution_ids":["https://openalex.org/I161024014"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5016512082","display_name":"Young-Ho Seo","orcid":"https://orcid.org/0000-0003-1046-395X","observed_orcids":["https://orcid.org/0000-0003-1046-395X"]},"institutions":[{"id":"https://openalex.org/I161024014","display_name":"Kwangwoon University","ror":"https://ror.org/02e9zc863","country_code":"KR","type":"education","lineage":["https://openalex.org/I161024014"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Young-Ho Seo","raw_affiliation_strings":["Department of Electronic Materials Engineering, Kwangwoon University, Seoul, South Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronic Materials Engineering, Kwangwoon University, Seoul, South Korea","institution_ids":["https://openalex.org/I161024014"]}]},{"author_position":"last","author":{"id":null,"display_name":"Dong-Wook Kim","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I161024014","display_name":"Kwangwoon University","ror":"https://ror.org/02e9zc863","country_code":"KR","type":"education","lineage":["https://openalex.org/I161024014"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Dong-Wook Kim","raw_affiliation_strings":["Department of Electronic Materials Engineering, Kwangwoon University, Seoul, South Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronic Materials Engineering, Kwangwoon University, Seoul, South Korea","institution_ids":["https://openalex.org/I161024014"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I161024014"],"apc_list":null,"apc_paid":null,"fwci":0.2293,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.39087794,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"332","last_page":"335"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.5625,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.5625,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.1923000067472458,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10743","display_name":"Software Testing and Debugging Techniques","score":0.12030000239610672,"subfield":{"id":"https://openalex.org/subfields/1712","display_name":"Software"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.7670000195503235},{"id":"https://openalex.org/keywords/design-verification","display_name":"design verification","score":0.7570000290870667},{"id":"https://openalex.org/keywords/pattern-generation","display_name":"pattern generation","score":0.7409999966621399},{"id":"https://openalex.org/keywords/error-localization","display_name":"error localization","score":0.5329999923706055}],"concepts":[{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.9017641544342041},{"id":"https://openalex.org/C55439883","wikidata":"https://www.wikidata.org/wiki/Q360812","display_name":"Correctness","level":2,"score":0.888203501701355},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7697204947471619},{"id":"https://openalex.org/C179518139","wikidata":"https://www.wikidata.org/wiki/Q5140297","display_name":"Coding (social sciences)","level":2,"score":0.6179722547531128},{"id":"https://openalex.org/C192328126","wikidata":"https://www.wikidata.org/wiki/Q4514647","display_name":"Schematic","level":2,"score":0.6052372455596924},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.484679251909256},{"id":"https://openalex.org/C138852830","wikidata":"https://www.wikidata.org/wiki/Q2292993","display_name":"Design methods","level":2,"score":0.45797181129455566},{"id":"https://openalex.org/C62460635","wikidata":"https://www.wikidata.org/wiki/Q5508853","display_name":"Functional verification","level":3,"score":0.4241117238998413},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3688358664512634},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.3565252125263214},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3509225845336914},{"id":"https://openalex.org/C111498074","wikidata":"https://www.wikidata.org/wiki/Q173326","display_name":"Formal verification","level":2,"score":0.31383591890335083},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.30805647373199463},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.2782180905342102},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.1936914622783661},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.09862300753593445},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.09644126892089844},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.09294193983078003},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/apasic.1999.824096","doi":"https://doi.org/10.1109/apasic.1999.824096","is_oa":false,"landing_page_url":"https://doi.org/10.1109/apasic.1999.824096","pdf_url":null,"source":{"id":"https://openalex.org/S4306502575","display_name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W127224647","https://openalex.org/W2006150400","https://openalex.org/W2090098281","https://openalex.org/W2100314073","https://openalex.org/W2103825248","https://openalex.org/W2122355433","https://openalex.org/W2132796821","https://openalex.org/W6684534873"],"related_works":["https://openalex.org/W2389148018","https://openalex.org/W2212688558","https://openalex.org/W2340490059","https://openalex.org/W2166246228","https://openalex.org/W2132796821","https://openalex.org/W2972181140","https://openalex.org/W12677450","https://openalex.org/W2000346290","https://openalex.org/W2137625054","https://openalex.org/W3016416170"],"abstract_inverted_index":{"Design":[0],"methodology":[1],"has":[2],"been":[3],"changing":[4],"from":[5,85],"schematic-based":[6],"design":[7,29,75,87,119],"to":[8,23,35,73],"HDL":[9,12],"based-design.":[10],"In":[11,45],"based-design,":[13],"coding":[14,41,59,90,104],"errors":[15],"may":[16],"exist":[17],"and":[18,26,64,76,88,96,101],"it":[19],"takes":[20],"much":[21],"time":[22],"be":[24],"found":[25],"corrected":[27],"in":[28,83,93],"process.":[30],"Thus":[31],"an":[32],"efficient":[33],"method":[34,52,99,112],"verify":[36,114],"the":[37,40,77,97,103,110,115,118],"correctness":[38,116],"of":[39,117],"itself":[42],"is":[43,60,81],"required.":[44],"this":[46],"paper,":[47],"we":[48],"proposed":[49,98,111],"a":[50],"verification":[51,65],"for":[53],"VHDL":[54,58,74,86,94],"behavioral":[55],"level":[56],"design.":[57],"converted":[61],"into":[62],"CDFG":[63],"patterns":[66,70],"are":[67,71],"generated.":[68],"Generated":[69],"applied":[72],"gold-unit.":[78],"If":[79],"there":[80],"difference":[82],"responses":[84],"gold-unit,":[89],"error":[91],"exists":[92],"design,":[95],"detects":[100],"locates":[102],"error.":[105],"Simulation":[106],"result":[107],"showed":[108],"that":[109],"could":[113],"efficiently.":[120]},"counts_by_year":[],"updated_date":"2026-11-04T10:54:05.112534","created_date":"2016-06-24T00:00:00"}