{"id":"https://openalex.org/W1582499752","doi":"https://doi.org/10.1109/isscc.1986.1156985","title":"A pattern matching processor array with defect tolerance","display_name":"A pattern matching processor array with defect tolerance","publication_year":1986,"publication_date":"1986-01-01","ids":{"openalex":"https://openalex.org/W1582499752","doi":"https://doi.org/10.1109/isscc.1986.1156985","mag":"1582499752"},"language":"en","primary_location":{"id":"doi:10.1109/isscc.1986.1156985","doi":"https://doi.org/10.1109/isscc.1986.1156985","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc.1986.1156985","pdf_url":null,"source":{"id":"https://openalex.org/S4210210374","display_name":"Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference","issn_l":"0193-6530","issn":["0193-6530","2376-8606"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core","norway-1"],"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","raw_type":"proceedings-article"},"volume":null,"type":"conference-paper","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5108190486","display_name":"T. Kawada","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I2251713219","display_name":"NTT (Japan)","ror":"https://ror.org/00berct97","country_code":"JP","type":"company","lineage":["https://openalex.org/I2251713219"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"T. Kawada","raw_affiliation_strings":["NTT Electrical Communication Laboratories, Tokyo, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"NTT Electrical Communication Laboratories, Tokyo, Japan","institution_ids":["https://openalex.org/I2251713219"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5043735152","display_name":"Yasuhiro Takahashi","orcid":"https://orcid.org/0000-0002-1653-8425","observed_orcids":["https://orcid.org/0000-0002-1653-8425"]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Y. Takahashi","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5035170998","display_name":"Nobuhiro TSUDA","orcid":null,"observed_orcids":[]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"N. Tsuda","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5087898280","display_name":"M. Waki","orcid":null,"observed_orcids":[]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"M. Waki","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"last","author":{"id":null,"display_name":"N. Hagiwara","orcid":null,"observed_orcids":[]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"N. Hagiwara","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.4134,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.51335878,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"90","last_page":"91"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12326","display_name":"Network Packet Processing and Optimization","score":0.15389999747276306,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12326","display_name":"Network Packet Processing and Optimization","score":0.15389999747276306,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.1468999981880188,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.11710000038146973,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/defect-tolerance","display_name":"defect tolerance","score":0.9860000014305115},{"id":"https://openalex.org/keywords/cmos-chip-design","display_name":"CMOS chip design","score":0.7300000190734863}],"concepts":[{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.7104523181915283},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6638123989105225},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.635486900806427},{"id":"https://openalex.org/C2780861071","wikidata":"https://www.wikidata.org/wiki/Q1062934","display_name":"Character (mathematics)","level":2,"score":0.5147857666015625},{"id":"https://openalex.org/C165064840","wikidata":"https://www.wikidata.org/wiki/Q1321061","display_name":"Matching (statistics)","level":2,"score":0.5024194717407227},{"id":"https://openalex.org/C83535845","wikidata":"https://www.wikidata.org/wiki/Q82772","display_name":"Kanji","level":3,"score":0.455474853515625},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.45416054129600525},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.43162304162979126},{"id":"https://openalex.org/C90805587","wikidata":"https://www.wikidata.org/wiki/Q10944557","display_name":"Word (group theory)","level":2,"score":0.4227622449398041},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.2902980446815491},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.21604818105697632},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.18793359398841858},{"id":"https://openalex.org/C2781051154","wikidata":"https://www.wikidata.org/wiki/Q8201","display_name":"Chinese characters","level":2,"score":0.11975982785224915},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.07416695356369019},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0683487057685852},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isscc.1986.1156985","doi":"https://doi.org/10.1109/isscc.1986.1156985","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc.1986.1156985","pdf_url":null,"source":{"id":"https://openalex.org/S4210210374","display_name":"Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference","issn_l":"0193-6530","issn":["0193-6530","2376-8606"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core","norway-1"],"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W1783600686","https://openalex.org/W2065723886","https://openalex.org/W2115005133","https://openalex.org/W1482562838","https://openalex.org/W2162001867","https://openalex.org/W2088965711","https://openalex.org/W2077882949","https://openalex.org/W2159741498","https://openalex.org/W1513469934","https://openalex.org/W1535754051"],"abstract_inverted_index":{"A":[0,36],"16b":[1],"processor":[2],"chip":[3],"with":[4],"sorter":[5],"and":[6,33],"32Kb":[7],"dictionary":[8],"RAM":[9],"has":[10],"been":[11],"developed":[12],"for":[13],"hand-printed":[14],"Kanji":[15],"character":[16],"recognition.":[17],"This":[18],"paper":[19],"will":[20],"describe":[21],"the":[22,31],"design":[23],"techniques":[24],"used":[25],"to":[26],"achieve":[27],"defect":[28],"tolerance":[29],"in":[30],"memory":[32],"logic":[34],"blocks.":[35],"18.5\u00d720.5mm2chip":[37],"contains":[38],"460,000":[39],"transistors":[40],"using":[41],"a":[42],"3\u03bcm":[43],"double":[44],"metal":[45],"CMOS":[46],"technology.":[47]},"counts_by_year":[],"updated_date":"2026-10-06T10:28:23.643775","created_date":"2016-06-24T00:00:00"}
