{"id":"https://openalex.org/W1533744962","doi":null,"title":"S-1 architecture manual","display_name":"S-1 architecture manual","publication_year":1979,"publication_date":"1979-01-01","ids":{"openalex":"https://openalex.org/W1533744962","mag":"1533744962"},"language":"en","primary_location":{"id":"mag:1533744962","doi":null,"is_oa":false,"landing_page_url":"https://dl.acm.org/citation.cfm?id=892205","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":null},"volume":null,"type":"article","is_traditional":true,"indexed_in":[],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5010121241","display_name":"Brent T. Hailpern","orcid":null,"observed_orcids":[]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Brent Hailpern","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"last","author":{"id":"https://openalex.org/A5090436298","display_name":"Bruce L. Hitson","orcid":null,"observed_orcids":[]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Bruce L. Hitson","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":0,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":2.7479,"has_fulltext":false,"cited_by_count":10,"citation_normalized_percentile":{"value":0.88681758,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.8949999809265137,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.8949999809265137,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10126","display_name":"Logic, programming, and type systems","score":0.02160000056028366,"subfield":{"id":"https://openalex.org/subfields/1712","display_name":"Software"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.018300000578165054,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/instruction-set-architecture","display_name":"instruction set architecture","score":0.8820000290870667},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"computer architecture","score":0.6899999976158142},{"id":"https://openalex.org/keywords/processor-instruction-set","display_name":"processor instruction set","score":0.3540000021457672}],"concepts":[{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.7319937348365784},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7013999819755554},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.5374529957771301},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.5226519107818604},{"id":"https://openalex.org/C79189994","wikidata":"https://www.wikidata.org/wiki/Q3488021","display_name":"Uniprocessor system","level":3,"score":0.45032185316085815},{"id":"https://openalex.org/C60048249","wikidata":"https://www.wikidata.org/wiki/Q37437","display_name":"Syntax","level":2,"score":0.4434535503387451},{"id":"https://openalex.org/C55356503","wikidata":"https://www.wikidata.org/wiki/Q2136675","display_name":"Reference architecture","level":4,"score":0.4171251654624939},{"id":"https://openalex.org/C115903868","wikidata":"https://www.wikidata.org/wiki/Q80993","display_name":"Software engineering","level":1,"score":0.40424904227256775},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.31916138529777527},{"id":"https://openalex.org/C35869016","wikidata":"https://www.wikidata.org/wiki/Q846636","display_name":"Software architecture","level":3,"score":0.23221322894096375},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.15378132462501526},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.12296280264854431},{"id":"https://openalex.org/C4822641","wikidata":"https://www.wikidata.org/wiki/Q846651","display_name":"Multiprocessing","level":2,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"mag:1533744962","doi":null,"is_oa":false,"landing_page_url":"https://dl.acm.org/citation.cfm?id=892205","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":null}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W3140674759","https://openalex.org/W220440441","https://openalex.org/W2016403210","https://openalex.org/W2000208782","https://openalex.org/W7096437332","https://openalex.org/W2100399943","https://openalex.org/W7039299893","https://openalex.org/W1491575491","https://openalex.org/W582113045","https://openalex.org/W2025521767"],"abstract_inverted_index":{"This":[0],"manual":[1,34],"provides":[2],"a":[3,27,40],"complete":[4],"description":[5],"of":[6,10,17,30],"the":[7,11,24,44,57,61],"instruction-set":[8],"architecture":[9,48],"S-1":[12,45,62],"Uniprocessor":[13],"(Mark":[14],"IIA),":[15],"exclusive":[16],"vector":[18],"operations.":[19],"It":[20],"is":[21],"assumed":[22],"that":[23],"reader":[25],"has":[26],"general":[28],"knowledge":[29],"computer":[31],"architecture.":[32],"The":[33],"was":[35],"designed":[36],"to":[37,43],"be":[38],"both":[39],"detailed":[41],"introduction":[42],"and":[46,60],"an":[47],"reference":[49],"manual.":[50],"Also":[51],"included":[52],"are":[53],"user":[54],"manuals":[55],"for":[56],"FASM":[58],"Assembler":[59],"Formal":[63],"Description":[64],"Syntax.":[65]},"counts_by_year":[],"updated_date":"2026-09-22T06:50:58.402377","created_date":"2016-06-24T00:00:00"}