{"id":"https://openalex.org/W1521268501","doi":null,"title":"Adiabatic Logic versus CMOS for Low Power Applications","display_name":"Adiabatic Logic versus CMOS for Low Power Applications","publication_year":2009,"publication_date":"2009-07-01","ids":{"openalex":"https://openalex.org/W1521268501","mag":"1521268501"},"language":"en","primary_location":{"id":"mag:1521268501","doi":null,"is_oa":false,"landing_page_url":"https://www1.gifu-u.ac.jp/~yasut/pdf/itc_paper2009.pdf","pdf_url":null,"source":{"id":"https://openalex.org/S4306498411","display_name":"International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":"ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications","raw_type":null},"volume":null,"type":"conference-paper","is_traditional":true,"indexed_in":[],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5067973102","display_name":"Nazrul Anuar Nayan","orcid":"https://orcid.org/0000-0001-6657-2982","observed_orcids":["https://orcid.org/0000-0001-6657-2982"]},"institutions":[{"id":"https://openalex.org/I42405503","display_name":"Gifu University","ror":"https://ror.org/024exxj48","country_code":"JP","type":"education","lineage":["https://openalex.org/I42405503"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Nazrul Anuar Nayan","raw_affiliation_strings":["Gifu Univ"],"raw_orcid":"https://orcid.org/0000-0001-6657-2982","affiliations":[{"raw_affiliation_string":"Gifu Univ","institution_ids":["https://openalex.org/I42405503"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5043735152","display_name":"Yasuhiro Takahashi","orcid":"https://orcid.org/0000-0002-1653-8425","observed_orcids":["https://orcid.org/0000-0002-1653-8425"]},"institutions":[{"id":"https://openalex.org/I42405503","display_name":"Gifu University","ror":"https://ror.org/024exxj48","country_code":"JP","type":"education","lineage":["https://openalex.org/I42405503"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Yasuhiro Takahashi","raw_affiliation_strings":["Gifu Univ"],"raw_orcid":"https://orcid.org/0000-0002-1653-8425","affiliations":[{"raw_affiliation_string":"Gifu Univ","institution_ids":["https://openalex.org/I42405503"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5108512806","display_name":"Toshikazu Sekine","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I42405503","display_name":"Gifu University","ror":"https://ror.org/024exxj48","country_code":"JP","type":"education","lineage":["https://openalex.org/I42405503"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Toshikazu Sekine","raw_affiliation_strings":["Gifu Univ"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Gifu Univ","institution_ids":["https://openalex.org/I42405503"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I42405503"],"apc_list":null,"apc_paid":null,"fwci":6.6051,"has_fulltext":false,"cited_by_count":31,"citation_normalized_percentile":{"value":0.97730781,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":88,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"302","last_page":"305"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.00039999998989515007,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13182","display_name":"Quantum-Dot Cellular Automata","score":0.00019999999494757503,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/adiabatic-logic","display_name":"adiabatic logic","score":0.9779999852180481},{"id":"https://openalex.org/keywords/two-phase-clocking","display_name":"two-phase clocking","score":0.6729999780654907},{"id":"https://openalex.org/keywords/energy-recovery","display_name":"energy recovery","score":0.718999981880188},{"id":"https://openalex.org/keywords/adiabatic-switching","display_name":"adiabatic switching","score":0.8169999718666077},{"id":"https://openalex.org/keywords/low-power-digital-circuits","display_name":"low-power digital circuits","score":0.7440000176429749},{"id":"https://openalex.org/keywords/energy-dissipation","display_name":"energy dissipation","score":0.656000018119812},{"id":"https://openalex.org/keywords/inverter","display_name":"inverter","score":0.5440000295639038},{"id":"https://openalex.org/keywords/nand-and-nor-gates","display_name":"NAND and NOR gates","score":0.718999981880188},{"id":"https://openalex.org/keywords/xor-gate","display_name":"XOR gate","score":0.800000011920929},{"id":"https://openalex.org/keywords/0-18-mum-cmos","display_name":"0.18 \u03bcm CMOS","score":0.718999981880188},{"id":"https://openalex.org/keywords/sensor-applications","display_name":"sensor applications","score":0.3919999897480011}],"concepts":[{"id":"https://openalex.org/C87606752","wikidata":"https://www.wikidata.org/wiki/Q4682637","display_name":"Adiabatic circuit","level":5,"score":0.859502911567688},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.7495735287666321},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.7206035256385803},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.6939783096313477},{"id":"https://openalex.org/C11190779","wikidata":"https://www.wikidata.org/wiki/Q664575","display_name":"Inverter","level":3,"score":0.635362982749939},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.6275453567504883},{"id":"https://openalex.org/C130126468","wikidata":"https://www.wikidata.org/wiki/Q4652943","display_name":"AND-OR-Invert","level":5,"score":0.5917990207672119},{"id":"https://openalex.org/C135402231","wikidata":"https://www.wikidata.org/wiki/Q898440","display_name":"Dissipation","level":2,"score":0.556627631187439},{"id":"https://openalex.org/C109663097","wikidata":"https://www.wikidata.org/wiki/Q182453","display_name":"Adiabatic process","level":2,"score":0.5394225120544434},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5315625071525574},{"id":"https://openalex.org/C124296912","wikidata":"https://www.wikidata.org/wiki/Q575178","display_name":"NAND gate","level":3,"score":0.519943118095398},{"id":"https://openalex.org/C146569638","wikidata":"https://www.wikidata.org/wiki/Q173378","display_name":"Logic level","level":3,"score":0.48267534375190735},{"id":"https://openalex.org/C2780077345","wikidata":"https://www.wikidata.org/wiki/Q16891888","display_name":"Spice","level":2,"score":0.4552061855792999},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.4530780017375946},{"id":"https://openalex.org/C61818909","wikidata":"https://www.wikidata.org/wiki/Q1987617","display_name":"Pull-up resistor","level":5,"score":0.43326476216316223},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.43047863245010376},{"id":"https://openalex.org/C7234692","wikidata":"https://www.wikidata.org/wiki/Q4116068","display_name":"NAND logic","level":4,"score":0.42740607261657715},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.41812440752983093},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.40778014063835144},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.3462640643119812},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3253488540649414},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.3033735752105713},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.20698308944702148},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.10872530937194824},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C97355855","wikidata":"https://www.wikidata.org/wiki/Q11473","display_name":"Thermodynamics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"mag:1521268501","doi":null,"is_oa":false,"landing_page_url":"https://www1.gifu-u.ac.jp/~yasut/pdf/itc_paper2009.pdf","pdf_url":null,"source":{"id":"https://openalex.org/S4306498411","display_name":"International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":"ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications","raw_type":null}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W138663297","https://openalex.org/W651605229","https://openalex.org/W1544558177","https://openalex.org/W2041255146","https://openalex.org/W2067139121","https://openalex.org/W2078813375","https://openalex.org/W2110148505","https://openalex.org/W2123299075","https://openalex.org/W2129886330","https://openalex.org/W2150363350"],"related_works":["https://openalex.org/W2015589098","https://openalex.org/W2122377402","https://openalex.org/W7096152237","https://openalex.org/W2008009631","https://openalex.org/W2106658792","https://openalex.org/W2186246884","https://openalex.org/W7095198646","https://openalex.org/W2244192522","https://openalex.org/W2027213168","https://openalex.org/W2330966479"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,11],"new":[4],"quasi":[5],"adiabatic":[6,33,43,149],"logic":[7,36,79,114,127,150],"family":[8],"that":[9],"uses":[10],"pair":[12],"of":[13,42,65,120,131],"complementary":[14],"split-level":[15],"sinusoidal":[16],"power":[17,23,63],"supply":[18],"clocks":[19],"for":[20],"digital":[21],"low":[22],"applications":[24],"such":[25],"as":[26],"sensors.":[27],"The":[28],"proposed":[29,147],"two":[30],"phase":[31],"clocked":[32],"static":[34,125],"CMOS":[35,90,126],"(2PASCL)":[37],"circuit":[38],"utilizes":[39],"the":[40,50,53,62,66,96,106,109,139],"principle":[41],"switching":[44],"and":[45,61,72,77],"energy":[46,121,142],"recovery.":[47],"By":[48],"removing":[49],"diode":[51,67],"at":[52,128],"charging":[54],"path,":[55],"higher":[56],"output":[57],"amplitude":[58],"is":[59,68,103],"achieved":[60],"consumption":[64],"eliminated.":[69],"We":[70],"design":[71],"simulate":[73],"NOT,":[74],"NAND,":[75],"NOR":[76],"Exclusive-OR":[78],"gates":[80],"based":[81],"on":[82],"2PASCL":[83,112],"with":[84,95,124,145],"SPICE":[85],"implemented":[86],"using":[87],"0.18":[88],"\u339b":[89],"technology.":[91],"A":[92],"driving":[93],"pulse":[94],"height":[97],"equal":[98],"to":[99,105,118,133],"V":[100],"dd":[101],"supplied":[104],"gates.":[107],"From":[108],"simulation":[110],"results,":[111],"inverter":[113],"can":[115],"save":[116],"up":[117],"97%":[119],"dissipation":[122,143],"compared":[123,144],"transition":[129],"frequencies":[130],"10":[132],"100":[134],"\u3392.":[135],"It":[136],"also":[137],"shows":[138],"lowest":[140],"in":[141],"other":[146],"simple":[148],"inverters.":[151]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2023,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":5},{"year":2014,"cited_by_count":5},{"year":2013,"cited_by_count":2}],"updated_date":"2026-10-31T12:09:11.096373","created_date":"2016-06-24T00:00:00"}
