{"id":"https://openalex.org/W15130301","doi":"https://doi.org/10.60713/pist-26033","title":"Timing issues in Cell Based VLSI design","display_name":"Timing issues in Cell Based VLSI design","publication_year":1990,"publication_date":"1990-01-01","ids":{"openalex":"https://openalex.org/W15130301","doi":"https://doi.org/10.60713/pist-26033","mag":"15130301"},"language":"en","primary_location":{"id":"doi:10.60713/pist-26033","doi":"https://doi.org/10.60713/pist-26033","is_oa":true,"landing_page_url":"https://doi.org/10.60713/pist-26033","pdf_url":null,"source":{"id":"https://openalex.org/S7407051441","display_name":"Tunisian Scientific and Technical Information Portal","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/I4392738169","host_organization_name":"University National Center of Scientific and Technical Documentation","host_organization_lineage":["https://openalex.org/I4392738169"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Dissertation"},"volume":null,"type":"dissertation","is_traditional":true,"indexed_in":["datacite"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://doi.org/10.60713/pist-26033","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5005819428","display_name":"Habib Youssef","orcid":"https://orcid.org/0000-0001-9189-2654","observed_orcids":["https://orcid.org/0000-0001-9189-2654"]},"institutions":[{"id":"https://openalex.org/I130238516","display_name":"University of Minnesota","ror":"https://ror.org/017zqws13","country_code":"US","type":"education","lineage":["https://openalex.org/I130238516"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Youssef, H.","raw_affiliation_strings":["University of Minnesota, Minneapolis,#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Minnesota, Minneapolis,#TAB#","institution_ids":["https://openalex.org/I130238516"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5005819428"],"corresponding_institution_ids":["https://openalex.org/I130238516"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9872999787330627,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9872999787330627,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.010700000450015068,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11661","display_name":"Copper Interconnects and Reliability","score":0.0003000000142492354,"subfield":{"id":"https://openalex.org/subfields/2504","display_name":"Electronic, Optical and Magnetic Materials"},"field":{"id":"https://openalex.org/fields/25","display_name":"Materials Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/interconnect-delay","display_name":"interconnect delay","score":0.9409999847412109},{"id":"https://openalex.org/keywords/latency-constraints","display_name":"delay constraints","score":0.6499999761581421},{"id":"https://openalex.org/keywords/timing-verification","display_name":"timing verification","score":0.47099998593330383},{"id":"https://openalex.org/keywords/physical-design","display_name":"physical design","score":0.7459999918937683},{"id":"https://openalex.org/keywords/cell-based-design","display_name":"cell-based design","score":0.5440000295639038}],"concepts":[{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.7568259835243225},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.7449688911437988},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7182376384735107},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.5213638544082642},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.5099536180496216},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.48667532205581665},{"id":"https://openalex.org/C90806461","wikidata":"https://www.wikidata.org/wiki/Q1144416","display_name":"Propagation delay","level":2,"score":0.4813404977321625},{"id":"https://openalex.org/C78401558","wikidata":"https://www.wikidata.org/wiki/Q464496","display_name":"Standard cell","level":3,"score":0.46518367528915405},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.4515787363052368},{"id":"https://openalex.org/C115874739","wikidata":"https://www.wikidata.org/wiki/Q825377","display_name":"Critical path method","level":2,"score":0.4279637336730957},{"id":"https://openalex.org/C166955791","wikidata":"https://www.wikidata.org/wiki/Q629579","display_name":"Macro","level":2,"score":0.4208006262779236},{"id":"https://openalex.org/C84434228","wikidata":"https://www.wikidata.org/wiki/Q4531332","display_name":"Elmore delay","level":4,"score":0.4198456406593323},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.41611248254776},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.38568350672721863},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.2851431369781494},{"id":"https://openalex.org/C174086752","wikidata":"https://www.wikidata.org/wiki/Q5253471","display_name":"Delay calculation","level":3,"score":0.27050432562828064},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.22790265083312988},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1446409821510315},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.60713/pist-26033","doi":"https://doi.org/10.60713/pist-26033","is_oa":true,"landing_page_url":"https://doi.org/10.60713/pist-26033","pdf_url":null,"source":{"id":"https://openalex.org/S7407051441","display_name":"Tunisian Scientific and Technical Information Portal","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/I4392738169","host_organization_name":"University National Center of Scientific and Technical Documentation","host_organization_lineage":["https://openalex.org/I4392738169"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Dissertation"},{"id":"mag:15130301","doi":null,"is_oa":false,"landing_page_url":"https://dl.acm.org/citation.cfm?id=101583","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":null}],"best_oa_location":{"id":"doi:10.60713/pist-26033","doi":"https://doi.org/10.60713/pist-26033","is_oa":true,"landing_page_url":"https://doi.org/10.60713/pist-26033","pdf_url":null,"source":{"id":"https://openalex.org/S7407051441","display_name":"Tunisian Scientific and Technical Information Portal","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/I4392738169","host_organization_name":"University National Center of Scientific and Technical Documentation","host_organization_lineage":["https://openalex.org/I4392738169"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Dissertation"},"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2053741873","https://openalex.org/W2134993085","https://openalex.org/W1543321007","https://openalex.org/W2523455619","https://openalex.org/W2525622615","https://openalex.org/W2153922782","https://openalex.org/W2293398285","https://openalex.org/W7099204936","https://openalex.org/W2107489001","https://openalex.org/W2036471109"],"abstract_inverted_index":{"With":[0],"the":[1,24,35,39,45,61,68,79,85,122,125,132,146,149,160,172,188,202,205,210,223,230,238,252,258,262,266,270,276,281,285,289],"advances":[2],"in":[3,44,60,67,78,261],"VLSI":[4],"design,":[5],"chip":[6],"timing":[7,82,133,226,253,291],"is":[8,90,129,138,273,301],"becoming":[9],"dominated":[10],"by":[11,93],"interconnect":[12,25],"delays":[13,26],"rather":[14],"than":[15,31],"macro":[16],"performances.":[17],"For":[18],"many":[19,98,184],"existing":[20,167],"large":[21],"computer":[22],"circuits,":[23],"already":[27],"account":[28],"for":[29,51,201,222,246],"more":[30],"a":[32,57,76,108,196],"half":[33],"of":[34,41,95,100,113,148,169,171,187,204,225,257,280,294],"clock":[36,62,102],"cycle,":[37],"and":[38,97,111,118,155,195,269],"portion":[40],"propagation":[42],"time":[43],"cycle":[46],"continues":[47],"to":[48,81,209,241,275,298],"grow.":[49],"Optimized":[50],"timing,":[52],"some":[53],"designs":[54,300],"can":[55],"permit":[56],"25-35%":[58],"increase":[59],"rate":[63],"without":[64],"any":[65,256],"changes":[66],"logic":[69],"or":[70],"cell":[71],"design.":[72,263],"This":[73,88],"fact":[74],"requires":[75],"change":[77],"approach":[80],"problems":[83],"through":[84],"design":[86,127,189,212,282],"process.":[87],"need":[89],"clearly":[91],"understood":[92],"designers":[94],"supercomputers":[96],"types":[99],"fast":[101],"electronics.\r\nIn":[103],"this":[104,144,295],"dissertation,":[105],"we":[106,164,215],"present":[107,216],"new":[109,197,218,233,296],"methodology":[110,198,297],"set":[112,147],"tools,":[114],"which":[115,190,248],"combine":[116],"verification":[117],"predictive":[119,141],"functions.":[120],"In":[121],"proposed":[123,200],"methodology,":[124],"physical":[126,211,278],"step":[128,279],"preceded":[130],"with":[131,140],"analysis":[134,137],"step.":[135,213],"Timing":[136],"augmented":[139],"capabilities.":[142],"During":[143],"step,":[145],"most":[150],"critical":[151,173,206,267],"paths":[152,174,207,260,268],"are":[153,162,175,199,235],"predicted,":[154],"delay":[156,244,271],"constraints":[157,227,254],"on":[158,228,237,255],"all":[159,229],"interconnects":[161],"computed.\r\nFirst":[163],"demonstrate":[165],"that":[166,284],"methodologies":[168],"identification":[170],"deficient":[176],"because":[177],"they":[178],"do":[179],"not":[180,250],"take":[181],"into":[182],"consideration":[183],"important":[185],"characteristics":[186],"influence":[191],"performance.":[192],"New":[193],"criteria":[194],"prediction":[203],"prior":[208],"Second,":[214],"several":[217],"polynomial":[219],"zero-slack":[220],"algorithms":[221,234],"computation":[224],"interconnects.":[231],"The":[232],"based":[236],"minimax":[239],"idea":[240],"identify":[242],"maximal":[243],"bounds":[245,272],"nets,":[247],"will":[249,287],"violate":[251],"logical":[259],"Information":[264],"about":[265],"supplied":[274],"next":[277],"so":[283],"layout":[286],"meet":[288],"pre-stated":[290],"requirements.":[292],"Application":[293],"real":[299],"demonstrated.":[302]},"counts_by_year":[],"updated_date":"2026-08-13T07:04:57.449891","created_date":"2016-06-24T00:00:00"}
