{"id":"https://openalex.org/W1494497668","doi":"https://doi.org/10.1109/esscirc.1988.5468357","title":"Sizing Algorithms for Linear Analog Circuits","display_name":"Sizing Algorithms for Linear Analog Circuits","publication_year":1988,"publication_date":"1988-09-01","ids":{"openalex":"https://openalex.org/W1494497668","doi":"https://doi.org/10.1109/esscirc.1988.5468357","mag":"1494497668"},"language":"en","primary_location":{"id":"doi:10.1109/esscirc.1988.5468357","doi":"https://doi.org/10.1109/esscirc.1988.5468357","is_oa":false,"landing_page_url":"https://doi.org/10.1109/esscirc.1988.5468357","pdf_url":null,"source":{"id":"https://openalex.org/S4210191203","display_name":"European Solid-State Circuits Conference (ESSCIRC)","issn_l":"1930-8833","issn":["1930-8833","2643-1319"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core","jufo-1","norway-1"],"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","raw_type":"proceedings-article"},"volume":null,"type":"conference-paper","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5071242717","display_name":"C. Meixenberger","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I135218257","display_name":"Swiss Center for Electronics and Microtechnology (Switzerland)","ror":"https://ror.org/05nrrsx06","country_code":"CH","type":"company","lineage":["https://openalex.org/I135218257"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"C. Meixenberger","raw_affiliation_strings":["CSEM, NEUCHATEL, Switzerland","CSEM, MALADIERE 71, CH-2000 NEUCHATEL"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"CSEM, NEUCHATEL, Switzerland","institution_ids":["https://openalex.org/I135218257"]},{"raw_affiliation_string":"CSEM, MALADIERE 71, CH-2000 NEUCHATEL","institution_ids":["https://openalex.org/I135218257"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5088044558","display_name":"B.L.A.G. Goffart","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I135218257","display_name":"Swiss Center for Electronics and Microtechnology (Switzerland)","ror":"https://ror.org/05nrrsx06","country_code":"CH","type":"company","lineage":["https://openalex.org/I135218257"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"B. Goffart","raw_affiliation_strings":["CSEM, NEUCHATEL, Switzerland","CSEM, MALADIERE 71, CH-2000 NEUCHATEL"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"CSEM, NEUCHATEL, Switzerland","institution_ids":["https://openalex.org/I135218257"]},{"raw_affiliation_string":"CSEM, MALADIERE 71, CH-2000 NEUCHATEL","institution_ids":["https://openalex.org/I135218257"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5085296624","display_name":"M. Pierre","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I135218257","display_name":"Swiss Center for Electronics and Microtechnology (Switzerland)","ror":"https://ror.org/05nrrsx06","country_code":"CH","type":"company","lineage":["https://openalex.org/I135218257"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"M. Pierre","raw_affiliation_strings":["CSEM, NEUCHATEL, Switzerland","CSEM, MALADIERE 71, CH-2000 NEUCHATEL"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"CSEM, NEUCHATEL, Switzerland","institution_ids":["https://openalex.org/I135218257"]},{"raw_affiliation_string":"CSEM, MALADIERE 71, CH-2000 NEUCHATEL","institution_ids":["https://openalex.org/I135218257"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5074205827","display_name":"M.G.R. Degrauwe","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I135218257","display_name":"Swiss Center for Electronics and Microtechnology (Switzerland)","ror":"https://ror.org/05nrrsx06","country_code":"CH","type":"company","lineage":["https://openalex.org/I135218257"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"M. Degrauwe","raw_affiliation_strings":["CSEM, NEUCHATEL, Switzerland","CSEM, MALADIERE 71, CH-2000 NEUCHATEL"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"CSEM, NEUCHATEL, Switzerland","institution_ids":["https://openalex.org/I135218257"]},{"raw_affiliation_string":"CSEM, MALADIERE 71, CH-2000 NEUCHATEL","institution_ids":["https://openalex.org/I135218257"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I135218257"],"apc_list":null,"apc_paid":null,"fwci":5.2689,"has_fulltext":false,"cited_by_count":10,"citation_normalized_percentile":{"value":0.94535975,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"190","last_page":"193"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9282000064849854,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9282000064849854,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.04390000179409981,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.012299999594688416,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/analog-circuit-sizing","display_name":"analog circuit sizing","score":0.7580000162124634},{"id":"https://openalex.org/keywords/linear-analog-circuits","display_name":"linear analog circuits","score":0.8299999833106995},{"id":"https://openalex.org/keywords/analog-synthesis","display_name":"analog synthesis","score":0.6240000128746033},{"id":"https://openalex.org/keywords/1-f-noise","display_name":"1/f noise","score":0.843999981880188},{"id":"https://openalex.org/keywords/component-sizing","display_name":"component sizing","score":0.6190000176429749},{"id":"https://openalex.org/keywords/operating-conditions","display_name":"operating conditions","score":0.34700000286102295}],"concepts":[{"id":"https://openalex.org/C2777767291","wikidata":"https://www.wikidata.org/wiki/Q1080291","display_name":"Sizing","level":2,"score":0.747910737991333},{"id":"https://openalex.org/C29074008","wikidata":"https://www.wikidata.org/wiki/Q174925","display_name":"Analogue electronics","level":3,"score":0.6898386478424072},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.6717639565467834},{"id":"https://openalex.org/C175291020","wikidata":"https://www.wikidata.org/wiki/Q1156822","display_name":"Offset (computer science)","level":2,"score":0.657638669013977},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6557936072349548},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.5218338370323181},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.47469040751457214},{"id":"https://openalex.org/C98142538","wikidata":"https://www.wikidata.org/wiki/Q485005","display_name":"Analog multiplier","level":4,"score":0.41784554719924927},{"id":"https://openalex.org/C2777212361","wikidata":"https://www.wikidata.org/wiki/Q5127848","display_name":"Class (philosophy)","level":2,"score":0.4130701720714569},{"id":"https://openalex.org/C13412647","wikidata":"https://www.wikidata.org/wiki/Q174948","display_name":"Analog signal","level":3,"score":0.29443979263305664},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1760106086730957},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1570340394973755},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.14336878061294556},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.07938900589942932},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.07501852512359619},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/esscirc.1988.5468357","doi":"https://doi.org/10.1109/esscirc.1988.5468357","is_oa":false,"landing_page_url":"https://doi.org/10.1109/esscirc.1988.5468357","pdf_url":null,"source":{"id":"https://openalex.org/S4210191203","display_name":"European Solid-State Circuits Conference (ESSCIRC)","issn_l":"1930-8833","issn":["1930-8833","2643-1319"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core","jufo-1","norway-1"],"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","raw_type":"proceedings-article"},{"id":"mag:3142174929","doi":null,"is_oa":false,"landing_page_url":"http://yadda.icm.edu.pl/yadda/element/bwmeta1.element.ieee-000005468357","pdf_url":null,"source":{"id":"https://openalex.org/S4210191203","display_name":"European Solid-State Circuits Conference (ESSCIRC)","issn_l":"1930-8833","issn":["1930-8833","2643-1319"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core","jufo-1","norway-1"],"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"conference"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":"European Solid-State Circuits Conference","raw_type":null}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2597714615","https://openalex.org/W2142024558","https://openalex.org/W2116235542","https://openalex.org/W7097723443","https://openalex.org/W2121456807","https://openalex.org/W2097003227","https://openalex.org/W2245004606","https://openalex.org/W7212085219","https://openalex.org/W2120670210","https://openalex.org/W2902462441"],"abstract_inverted_index":{"Basic":[0],"sizing":[1],"routines":[2,17,41],"of":[3,16,24,37,45],"a":[4,34,56],"synthesis":[5],"program":[6],"for":[7,33],"MOS":[8],"analog":[9,31],"circuits":[10,63],"[1]":[11],"are":[12],"presented.":[13],"A":[14],"class":[15],"is":[18,72],"given":[19],"that":[20],"allows":[21],"the":[22],"design":[23],"single":[25],"components":[26],"as":[27,29,49],"well":[28],"basic":[30],"structures":[32],"large":[35],"domain":[36],"operating":[38],"conditions.":[39],"These":[40],"can":[42],"have":[43],"any":[44],"their":[46],"characteristics":[47],"imposed":[48],"input":[50],"parameters":[51],"or":[52],"output":[53],"variables.":[54],"Moreover,":[55],"general":[57],"valid":[58],"routine":[59],"useful":[60],"to":[61,65],"size":[62],"according":[64],"1/f":[66],"noise,":[67],"offset":[68],"and":[69],"gain":[70],"specifications":[71],"given.":[73]},"counts_by_year":[],"updated_date":"2026-10-31T12:09:11.096373","created_date":"2016-06-24T00:00:00"}
