{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","description":"This cluster of papers focuses on advances in reconfigurable computing systems and design methods, including topics such as high-level synthesis, system-level design, FPGA architectures, multiprocessor SoCs, dynamic reconfiguration, hardware/software codesign, dataflow programming languages, and platform-based design.","keywords":[{"id":"https://openalex.org/keywords/fpga","display_name":"FPGA","score":0.2335},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"high-level synthesis","score":0.7491},{"id":"https://openalex.org/keywords/hardware-software-co-design","display_name":"hardware-software co-design","score":0.5063},{"id":"https://openalex.org/keywords/system-on-chip","display_name":"system-on-chip","score":0.2792},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"reconfigurable computing","score":0.6219},{"id":"https://openalex.org/keywords/hardware-description-languages","display_name":"hardware description languages","score":0.4395},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"design space exploration","score":0.2552},{"id":"https://openalex.org/keywords/hardware-acceleration","display_name":"hardware acceleration","score":0.2548},{"id":"https://openalex.org/keywords/reconfigurable-hardware","display_name":"reconfigurable hardware","score":0.3573},{"id":"https://openalex.org/keywords/systemc","display_name":"SystemC","score":0.7501},{"id":"https://openalex.org/keywords/dynamic-reconfiguration","display_name":"dynamic reconfiguration","score":0.2795},{"id":"https://openalex.org/keywords/multi-processor-systems-on-chip","display_name":"MPSoC","score":0.4942},{"id":"https://openalex.org/keywords/hardware-synthesis","display_name":"hardware synthesis","score":0.535},{"id":"https://openalex.org/keywords/hardware-accelerators","display_name":"hardware accelerators","score":0.2811},{"id":"https://openalex.org/keywords/hardware-software-partitioning","display_name":"hardware/software partitioning","score":0.8068},{"id":"https://openalex.org/keywords/embedded-processors","display_name":"embedded processors","score":0.2794},{"id":"https://openalex.org/keywords/system-level-design","display_name":"system-level design","score":0.4498},{"id":"https://openalex.org/keywords/fpga-accelerator","display_name":"FPGA accelerator","score":0.4855},{"id":"https://openalex.org/keywords/hardware-verification","display_name":"hardware verification","score":0.2492},{"id":"https://openalex.org/keywords/risc-v","display_name":"RISC-V","score":0.2923},{"id":"https://openalex.org/keywords/embedded-system-design","display_name":"embedded system design","score":0.2096},{"id":"https://openalex.org/keywords/fpga-acceleration","display_name":"FPGA acceleration","score":0.4037},{"id":"https://openalex.org/keywords/soc-design","display_name":"system-on-chip design","score":0.5576},{"id":"https://openalex.org/keywords/reconfigurable-architecture","display_name":"reconfigurable architecture","score":0.3816},{"id":"https://openalex.org/keywords/application-specific-instruction-set-processors","display_name":"application-specific instruction set processors","score":0.705}],"legacy_keywords":"Reconfigurable Computing; High-Level Synthesis; System-Level Design; FPGA; Multiprocessor SoC; Embedded Systems; Dynamic Reconfiguration; Hardware/Software Codesign; Dataflow Programming Languages; Platform-Based Design","ids":{"openalex":"https://openalex.org/T10904","wikipedia":"https://en.wikipedia.org/wiki/Reconfigurable_computing"},"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"},"siblings":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques"},{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling"},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing"},{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security"},{"id":"https://openalex.org/T12326","display_name":"Network Packet Processing and Optimization"},{"id":"https://openalex.org/T14067","display_name":"Cloud Computing and Remote Desktop Technologies"},{"id":"https://openalex.org/T14098","display_name":"Energy Efficiency in Computing"}],"works_count":112257,"cited_by_count":668178,"works_api_url":"https://api.openalex.org/works?filter=topics.id:T10904","updated_date":"2026-10-22T03:01:35","created_date":"2024-01-23T15:27:08"}