{"id":"https://openalex.org/keywords/wirelength-minimization","display_name":"wirelength minimization","description":"Wirelength minimization is an optimization objective in very-large-scale integrated circuit design that reduces the total length of interconnects between components.","display_name_alternatives":["wirelength minimisation","wire length minimisation","minimization of wirelength","wirelength reduction","wire length reduction","interconnect length minimization","total wirelength minimization","wire length minimization"],"ids":{"openalex":"https://openalex.org/keywords/wirelength-minimization","wikidata":null},"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.7795,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.7795,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.1136,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"works_count":1753,"cited_by_count":26589,"works_api_url":"https://api.openalex.org/works?filter=keywords.id:keywords/wirelength-minimization","updated_date":"2026-10-19T04:06:21","created_date":"2026-09-30T00:00:00"}