{"id":"https://openalex.org/A5148766388","orcid":"https://orcid.org/0009-0002-3245-1810","observed_orcids":["https://orcid.org/0009-0002-3245-1810"],"display_name":"Jingyi Zhou","raw_author_names":["Jingyi Zhou","Zhou, Jingyi"],"full_name":"Jingyi Zhou","works_count":3,"cited_by_count":0,"summary_stats":{"2yr_mean_citedness":0.0,"h_index":0,"i10_index":0},"ids":{"openalex":"https://openalex.org/A5148766388","orcid":"https://orcid.org/0009-0002-3245-1810","observed_orcids":["https://orcid.org/0009-0002-3245-1810"]},"affiliations":[{"institution":{"id":"https://openalex.org/I177725633","ror":"https://ror.org/00t33hh48","display_name":"Chinese University of Hong Kong","country_code":"HK","type":"education","lineage":["https://openalex.org/I177725633"]},"years":[2026]},{"institution":{"id":"https://openalex.org/I99065089","ror":"https://ror.org/03cve4549","display_name":"Tsinghua University","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]},"years":[2026]}],"last_known_institutions":[{"id":"https://openalex.org/I177725633","ror":"https://ror.org/00t33hh48","display_name":"Chinese University of Hong Kong","country_code":"HK","type":"education","lineage":["https://openalex.org/I177725633"]},{"id":"https://openalex.org/I99065089","ror":"https://ror.org/03cve4549","display_name":"Tsinghua University","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","count":3,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","count":3,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","count":1,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","count":1,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11273","display_name":"Advanced Graph Neural Networks","count":1,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"topic_share":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","value":1.43e-05,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11273","display_name":"Advanced Graph Neural Networks","value":1.25e-05,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","value":9.2e-06,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","value":3.7e-06,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","value":3.4e-06,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"x_concepts":[{"id":"132525143","wikidata":"https://www.wikidata.org/wiki/Q141488","display_name":"Graph","score":0.5254999995231628},{"id":"2776359362","wikidata":"https://www.wikidata.org/wiki/Q2145286","display_name":"Representation (politics)","score":0.5001999735832214},{"id":"108583219","wikidata":"https://www.wikidata.org/wiki/Q197536","display_name":"Deep learning","score":0.4754999876022339},{"id":"154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","score":0.4512999951839447},{"id":"11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","score":0.28929999470710754}],"counts_by_year":[{"year":2026,"works_count":3,"oa_works_count":3,"cited_by_count":0}],"display_name_alternatives":["Jingyi Zhou","Zhou, Jingyi"],"block_key":"j zhou","works_api_url":"https://api.openalex.org/works?filter=author.id:A5148766388","updated_date":"2026-11-01T11:00:13","created_date":"2025-10-10T00:00:00"}
