{"id":"https://openalex.org/A5126847282","orcid":"https://orcid.org/0000-0002-2186-9579","observed_orcids":["https://orcid.org/0000-0002-2186-9579"],"display_name":"Zhengyuan Shi","raw_author_names":["Shi, Zhengyuan","Zhengyuan Shi"],"full_name":"Shi, Zhengyuan","works_count":5,"cited_by_count":0,"summary_stats":{"2yr_mean_citedness":0.0,"h_index":0,"i10_index":0},"ids":{"openalex":"https://openalex.org/A5126847282","orcid":"https://orcid.org/0000-0002-2186-9579","observed_orcids":["https://orcid.org/0000-0002-2186-9579"]},"affiliations":[{"institution":{"id":"https://openalex.org/I177725633","ror":"https://ror.org/00t33hh48","display_name":"Chinese University of Hong Kong","country_code":"HK","type":"education","lineage":["https://openalex.org/I177725633"]},"years":[2026]}],"last_known_institutions":[{"id":"https://openalex.org/I177725633","ror":"https://ror.org/00t33hh48","display_name":"Chinese University of Hong Kong","country_code":"HK","type":"education","lineage":["https://openalex.org/I177725633"]}],"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","count":4,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","count":3,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","count":3,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","count":2,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10126","display_name":"Logic, programming, and type systems","count":1,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"topic_share":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","value":1.91e-05,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11596","display_name":"Constraint Satisfaction and Optimization","value":1.16e-05,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","value":1.11e-05,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","value":1e-05,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","value":9.2e-06,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"x_concepts":[{"id":"41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","score":0.7281000018119812},{"id":"80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","score":0.6085000038146973},{"id":"157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","score":0.5684000253677368},{"id":"11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","score":0.534600019454956},{"id":"111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","score":0.4959000051021576}],"counts_by_year":[{"year":2026,"works_count":5,"oa_works_count":5,"cited_by_count":0}],"display_name_alternatives":["Shi, Zhengyuan","Zhengyuan Shi"],"block_key":"z shi","works_api_url":"https://api.openalex.org/works?filter=author.id:A5126847282","updated_date":"2026-11-01T11:00:13","created_date":"2026-01-23T00:00:00"}