{"id":"https://openalex.org/A5122953443","orcid":null,"observed_orcids":[],"display_name":"Chenhui Deng","raw_author_names":["Chenhui Deng","Deng, Chenhui"],"full_name":"Deng, Chenhui","works_count":6,"cited_by_count":80,"summary_stats":{"2yr_mean_citedness":13.333333333333334,"h_index":4,"i10_index":3},"ids":{"openalex":"https://openalex.org/A5122953443","orcid":null,"observed_orcids":[]},"affiliations":[{"institution":{"id":"https://openalex.org/I1304085615","ror":"https://ror.org/02kr42612","display_name":"Nvidia (United Kingdom)","country_code":"GB","type":"company","lineage":["https://openalex.org/I1304085615","https://openalex.org/I4210127875"]},"years":[2026]},{"institution":{"id":"https://openalex.org/I4210127875","ror":"https://ror.org/03jdj4y14","display_name":"Nvidia (United States)","country_code":"US","type":"company","lineage":["https://openalex.org/I4210127875"]},"years":[2026]}],"last_known_institutions":[{"id":"https://openalex.org/I1304085615","ror":"https://ror.org/02kr42612","display_name":"Nvidia (United Kingdom)","country_code":"GB","type":"company","lineage":["https://openalex.org/I1304085615","https://openalex.org/I4210127875"]},{"id":"https://openalex.org/I4210127875","ror":"https://ror.org/03jdj4y14","display_name":"Nvidia (United States)","country_code":"US","type":"company","lineage":["https://openalex.org/I4210127875"]}],"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","count":5,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","count":4,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10260","display_name":"Software Engineering Research","count":2,"subfield":{"id":"https://openalex.org/subfields/1710","display_name":"Information Systems"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10028","display_name":"Topic Modeling","count":1,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10181","display_name":"Natural Language Processing Techniques","count":1,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"topic_share":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","value":2.01e-05,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","value":1.61e-05,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","value":1.04e-05,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11975","display_name":"Evolutionary Algorithms and Applications","value":7.2e-06,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11714","display_name":"Multimodal Machine Learning Applications","value":7.1e-06,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"x_concepts":[{"id":"41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","score":0.810699999332428},{"id":"26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","score":0.5917999744415283},{"id":"154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","score":0.5885000228881836},{"id":"199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","score":0.4943000078201294},{"id":"149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","score":0.43549999594688416}],"counts_by_year":[{"year":2025,"works_count":0,"oa_works_count":0,"cited_by_count":1},{"year":2026,"works_count":6,"oa_works_count":6,"cited_by_count":79}],"display_name_alternatives":["Chenhui Deng","Deng, Chenhui"],"block_key":"c deng","works_api_url":"https://api.openalex.org/works?filter=author.id:A5122953443","updated_date":"2026-11-07T12:08:38","created_date":"2026-02-13T00:00:00"}