{"id":"https://openalex.org/A5113333693","orcid":null,"observed_orcids":[],"display_name":"Jiahang Lou","raw_author_names":["Jiahang Lou","Jiahang, Lou","Lou, Jiahang"],"full_name":"Lou, Jiahang","works_count":9,"cited_by_count":15,"summary_stats":{"2yr_mean_citedness":1.6666666666666667,"h_index":2,"i10_index":0},"ids":{"openalex":"https://openalex.org/A5113333693","orcid":null,"observed_orcids":[]},"affiliations":[{"institution":{"id":"https://openalex.org/I24943067","ror":"https://ror.org/013q1eq08","display_name":"Fudan University","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]},"years":[2026,2025,2024]},{"institution":{"id":"https://openalex.org/I4391767673","ror":"https://ror.org/01mamgv83","display_name":"State Key Laboratory of ASIC and System","country_code":null,"type":"facility","lineage":["https://openalex.org/I24943067","https://openalex.org/I4391767673"]},"years":[2024]}],"last_known_institutions":[{"id":"https://openalex.org/I24943067","ror":"https://ror.org/013q1eq08","display_name":"Fudan University","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","count":9,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","count":7,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","count":6,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","count":2,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10036","display_name":"Advanced Neural Network Applications","count":1,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"topic_share":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","value":3.97e-05,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","value":3.41e-05,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","value":2.82e-05,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","value":6e-06,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","value":3.5e-06,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"x_concepts":[{"id":"41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","score":0.8680999875068665},{"id":"123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","score":0.70931476354599},{"id":"173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","score":0.6371999979019165},{"id":"118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","score":0.5511189103126526},{"id":"149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","score":0.40959998965263367}],"counts_by_year":[{"year":2024,"works_count":3,"oa_works_count":0,"cited_by_count":13},{"year":2025,"works_count":1,"oa_works_count":0,"cited_by_count":2},{"year":2026,"works_count":5,"oa_works_count":3,"cited_by_count":0}],"display_name_alternatives":["Jiahang Lou","Jiahang, Lou","Lou, Jiahang"],"block_key":"j lou","works_api_url":"https://api.openalex.org/works?filter=author.id:A5113333693","updated_date":"2026-10-12T12:34:37","created_date":"2025-10-10T00:00:00"}