{"id":"https://openalex.org/A5111370703","orcid":null,"observed_orcids":[],"display_name":"Asheesh Khare","raw_author_names":["Asheesh Khare"],"full_name":"Asheesh Khare","works_count":8,"cited_by_count":443,"summary_stats":{"2yr_mean_citedness":0.0,"h_index":4,"i10_index":3},"ids":{"openalex":"https://openalex.org/A5111370703","orcid":null,"observed_orcids":[]},"affiliations":[{"institution":{"id":"https://openalex.org/I204250578","ror":"https://ror.org/04gyf1771","display_name":"University of California, Irvine","country_code":"US","type":"education","lineage":["https://openalex.org/I204250578"]},"years":[2008,2001,1999]}],"last_known_institutions":[{"id":"https://openalex.org/I204250578","ror":"https://ror.org/04gyf1771","display_name":"University of California, Irvine","country_code":"US","type":"education","lineage":["https://openalex.org/I204250578"]}],"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","count":8,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","count":8,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","count":4,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","count":2,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10639","display_name":"Advanced Software Engineering Methodologies","count":1,"subfield":{"id":"https://openalex.org/subfields/1712","display_name":"Software"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"topic_share":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","value":4.02e-05,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","value":2.72e-05,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","value":2.57e-05,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13292","display_name":"Embedded Systems and FPGA Applications","value":5.8e-06,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","value":3.6e-06,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"x_concepts":[{"id":"41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","score":0.8737677335739136},{"id":"123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","score":0.6713327169418335},{"id":"118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","score":0.6542488932609558},{"id":"149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","score":0.5867000222206116},{"id":"26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","score":0.5455202460289001}],"counts_by_year":[{"year":1998,"works_count":2,"oa_works_count":0,"cited_by_count":0},{"year":1999,"works_count":4,"oa_works_count":0,"cited_by_count":0},{"year":2001,"works_count":1,"oa_works_count":0,"cited_by_count":0},{"year":2008,"works_count":1,"oa_works_count":0,"cited_by_count":0},{"year":2012,"works_count":0,"oa_works_count":0,"cited_by_count":20},{"year":2013,"works_count":0,"oa_works_count":0,"cited_by_count":14},{"year":2014,"works_count":0,"oa_works_count":0,"cited_by_count":10},{"year":2015,"works_count":0,"oa_works_count":0,"cited_by_count":4},{"year":2016,"works_count":0,"oa_works_count":0,"cited_by_count":6},{"year":2017,"works_count":0,"oa_works_count":0,"cited_by_count":4},{"year":2018,"works_count":0,"oa_works_count":0,"cited_by_count":1},{"year":2019,"works_count":0,"oa_works_count":0,"cited_by_count":3},{"year":2020,"works_count":0,"oa_works_count":0,"cited_by_count":2},{"year":2021,"works_count":0,"oa_works_count":0,"cited_by_count":4},{"year":2022,"works_count":0,"oa_works_count":0,"cited_by_count":2},{"year":2023,"works_count":0,"oa_works_count":0,"cited_by_count":2},{"year":2024,"works_count":0,"oa_works_count":0,"cited_by_count":1},{"year":2025,"works_count":0,"oa_works_count":0,"cited_by_count":4},{"year":2026,"works_count":0,"oa_works_count":0,"cited_by_count":1}],"display_name_alternatives":["Asheesh Khare"],"block_key":"a khare","works_api_url":"https://api.openalex.org/works?filter=author.id:A5111370703","awards_count":0,"updated_date":"2026-11-07T12:08:38","created_date":"2016-06-24T00:00:00"}
