{"id":"https://openalex.org/A5020161854","orcid":null,"observed_orcids":[],"display_name":"P. Poechmueller","raw_author_names":["P. POECHMUELLER","P. Pochmuller","P. Poechmueller","Peter Poechmueller","Peter P\u00f6chm\u00fcller","P\u00f6chm\u00fcller, Peter"],"full_name":"Peter Poechmueller","works_count":28,"cited_by_count":99,"summary_stats":{"2yr_mean_citedness":0.3333333333333333,"h_index":5,"i10_index":3},"ids":{"openalex":"https://openalex.org/A5020161854","orcid":null,"observed_orcids":[]},"affiliations":[{"institution":{"id":"https://openalex.org/I1341412227","ror":"https://ror.org/05hh8d621","display_name":"IBM (United States)","country_code":"US","type":"company","lineage":["https://openalex.org/I1341412227"]},"years":[2004,2002,1999,1996]},{"institution":{"id":"https://openalex.org/I31512782","ror":"https://ror.org/05n911h24","display_name":"Technische Universit\u00e4t Darmstadt","country_code":"DE","type":"education","lineage":["https://openalex.org/I31512782"]},"years":[2003,2002,1993,1991]},{"institution":{"id":"https://openalex.org/I4210144190","ror":"https://ror.org/04e4db319","display_name":"Infineon Technologies (United States)","country_code":"US","type":"company","lineage":["https://openalex.org/I137594350","https://openalex.org/I4210144190"]},"years":[2003]}],"last_known_institutions":null,"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","count":18,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","count":16,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","count":10,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","count":7,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","count":6,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"topic_share":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","value":8.04e-05,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","value":5.79e-05,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","value":3.52e-05,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","value":3.13e-05,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","value":2.83e-05,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"x_concepts":[{"id":"41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","score":0.8347328901290894},{"id":"118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","score":0.6701573133468628},{"id":"149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","score":0.6093900203704834},{"id":"127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","score":0.5397999882698059},{"id":"111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","score":0.45559999346733093}],"counts_by_year":[{"year":1991,"works_count":3,"oa_works_count":0,"cited_by_count":0},{"year":1993,"works_count":4,"oa_works_count":0,"cited_by_count":0},{"year":1995,"works_count":1,"oa_works_count":0,"cited_by_count":0},{"year":1996,"works_count":2,"oa_works_count":0,"cited_by_count":0},{"year":1998,"works_count":1,"oa_works_count":0,"cited_by_count":0},{"year":1999,"works_count":1,"oa_works_count":0,"cited_by_count":0},{"year":2002,"works_count":7,"oa_works_count":0,"cited_by_count":0},{"year":2003,"works_count":5,"oa_works_count":0,"cited_by_count":0},{"year":2004,"works_count":1,"oa_works_count":0,"cited_by_count":0},{"year":2012,"works_count":0,"oa_works_count":0,"cited_by_count":3},{"year":2013,"works_count":0,"oa_works_count":0,"cited_by_count":2},{"year":2015,"works_count":0,"oa_works_count":0,"cited_by_count":1},{"year":2016,"works_count":0,"oa_works_count":0,"cited_by_count":4},{"year":2017,"works_count":0,"oa_works_count":0,"cited_by_count":4},{"year":2018,"works_count":0,"oa_works_count":0,"cited_by_count":1},{"year":2019,"works_count":0,"oa_works_count":0,"cited_by_count":2},{"year":2020,"works_count":0,"oa_works_count":0,"cited_by_count":1},{"year":2021,"works_count":0,"oa_works_count":0,"cited_by_count":1},{"year":2022,"works_count":0,"oa_works_count":0,"cited_by_count":1},{"year":2023,"works_count":0,"oa_works_count":0,"cited_by_count":1},{"year":2024,"works_count":1,"oa_works_count":0,"cited_by_count":0},{"year":2025,"works_count":1,"oa_works_count":1,"cited_by_count":0},{"year":2026,"works_count":1,"oa_works_count":1,"cited_by_count":1}],"display_name_alternatives":["P. POECHMUELLER","P. Pochmuller","P. Poechmueller","Peter Poechmueller","Peter P\u00f6chm\u00fcller","P\u00f6chm\u00fcller, Peter"],"block_key":"p poechmueller","works_api_url":"https://api.openalex.org/works?filter=author.id:A5020161854","awards_count":0,"awards_api_url":"https://api.openalex.org/awards?filter=investigators.author.id:A5020161854","updated_date":"2026-11-12T13:17:38","created_date":"2016-06-24T00:00:00"}
