{"id":"https://openalex.org/A5000812243","orcid":null,"observed_orcids":[],"display_name":"Z. Amitai","raw_author_names":["Z. Amitai"],"full_name":"Z. Amitai","works_count":12,"cited_by_count":0,"summary_stats":{"2yr_mean_citedness":0.0,"h_index":0,"i10_index":0},"ids":{"openalex":"https://openalex.org/A5000812243","orcid":null,"observed_orcids":[]},"affiliations":[{"institution":{"id":"https://openalex.org/I27804330","ror":"https://ror.org/05gq02987","display_name":"Brown University","country_code":"US","type":"education","lineage":["https://openalex.org/I27804330"]},"years":[2005]},{"institution":{"id":"https://openalex.org/I4210150981","ror":"https://ror.org/051vpgk97","display_name":"Toshiba (United States)","country_code":"US","type":"company","lineage":["https://openalex.org/I1292669757","https://openalex.org/I4210150981"]},"years":[2002]}],"last_known_institutions":[{"id":"https://openalex.org/I27804330","ror":"https://ror.org/05gq02987","display_name":"Brown University","country_code":"US","type":"education","lineage":["https://openalex.org/I27804330"]}],"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","count":9,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","count":6,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12326","display_name":"Network Packet Processing and Optimization","count":5,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","count":4,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","count":4,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"topic_share":[{"id":"https://openalex.org/T12326","display_name":"Network Packet Processing and Optimization","value":3.92e-05,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","value":3.18e-05,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","value":2.02e-05,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","value":1.36e-05,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13436","display_name":"Space Technology and Applications","value":1.21e-05,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"x_concepts":[{"id":"41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","score":0.830092191696167},{"id":"149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","score":0.48762384057044983},{"id":"118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","score":0.47450894117355347},{"id":"9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","score":0.40735000371932983},{"id":"127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","score":0.2368048131465912}],"counts_by_year":[{"year":1991,"works_count":4,"oa_works_count":0,"cited_by_count":0},{"year":2002,"works_count":7,"oa_works_count":0,"cited_by_count":0},{"year":2005,"works_count":1,"oa_works_count":0,"cited_by_count":0}],"display_name_alternatives":["Z. Amitai"],"block_key":"z amitai","works_api_url":"https://api.openalex.org/works?filter=author.id:A5000812243","awards_count":0,"updated_date":"2026-10-28T12:34:19","created_date":"2016-06-24T00:00:00"}
